A High-Throughput QC-LDPC Decoder for Near-Earth Application
Turbo-like decoding message passing (TDMP) scheduling, which is suitable for quasi-cyclic low-density parity-check (QC-LDPC) codes, can obtain better decoding performance and shorter convergence time than two-phase message passing (TPMP). Normalized min-sum algorithm (NMSA) is used to reduce complex...
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| Veröffentlicht in: | International Conference on Digital Signal Processing proceedings S. 1 - 4 |
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01.11.2018
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| ISSN: | 2165-3577 |
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| Abstract | Turbo-like decoding message passing (TDMP) scheduling, which is suitable for quasi-cyclic low-density parity-check (QC-LDPC) codes, can obtain better decoding performance and shorter convergence time than two-phase message passing (TPMP). Normalized min-sum algorithm (NMSA) is used to reduce complexity of soft message processing unit. In this paper, we propose a (8176, 7154) QC-LDPC decoder for Consultative Committee for Space Data Systems (CCSDS) standard. In order to avoid memory access conflicts, two cyclic-shifted identity matrices forming a submatrix are processed individually. The decoder is synthesized by TSMC 65nm CMOS process and can achieve a throughput of 4.1Gb/s at clock frequency of 380MHz. |
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| AbstractList | Turbo-like decoding message passing (TDMP) scheduling, which is suitable for quasi-cyclic low-density parity-check (QC-LDPC) codes, can obtain better decoding performance and shorter convergence time than two-phase message passing (TPMP). Normalized min-sum algorithm (NMSA) is used to reduce complexity of soft message processing unit. In this paper, we propose a (8176, 7154) QC-LDPC decoder for Consultative Committee for Space Data Systems (CCSDS) standard. In order to avoid memory access conflicts, two cyclic-shifted identity matrices forming a submatrix are processed individually. The decoder is synthesized by TSMC 65nm CMOS process and can achieve a throughput of 4.1Gb/s at clock frequency of 380MHz. |
| Author | Chen, Yun Zeng, Xiaoyang Zhang, Qichen Li, Shixian |
| Author_xml | – sequence: 1 givenname: Shixian surname: Li fullname: Li, Shixian organization: State Key Laboratory of ASIC and system, Fudan University, Shanghai, 200433, CHINA – sequence: 2 givenname: Qichen surname: Zhang fullname: Zhang, Qichen organization: State Key Laboratory of ASIC and system, Fudan University, Shanghai, 200433, CHINA – sequence: 3 givenname: Yun surname: Chen fullname: Chen, Yun organization: State Key Laboratory of ASIC and system, Fudan University, Shanghai, 200433, CHINA – sequence: 4 givenname: Xiaoyang surname: Zeng fullname: Zeng, Xiaoyang organization: State Key Laboratory of ASIC and system, Fudan University, Shanghai, 200433, CHINA |
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| Snippet | Turbo-like decoding message passing (TDMP) scheduling, which is suitable for quasi-cyclic low-density parity-check (QC-LDPC) codes, can obtain better decoding... |
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| SubjectTerms | Clocks Computer architecture cyclic-shifted identity matrix Decoder architecture Decoding Hardware Manganese normalized min-sum algorithm (NMSA) Parity check codes quasi-cyclic low-density parity-check (QC-LDPC) Throughput turbo-decoding message-passing (TDMP) |
| Title | A High-Throughput QC-LDPC Decoder for Near-Earth Application |
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