CNP: An FPGA-based processor for Convolutional Networks

Convolutional networks (ConvNets) are biologically inspired hierarchical architectures that can be trained to perform a variety of detection, recognition and segmentation tasks. ConvNets have a feed-forward architecture consisting of multiple linear convolution filters interspersed with pointwise no...

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Veröffentlicht in:International Conference on Field-programmable Logic and Applications S. 32 - 37
Hauptverfasser: Farabet, C., Poulet, C., Han, J.Y., LeCun, Y.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.08.2009
Schlagworte:
Cameras
Convolution
Face detection
Feedforward systems
Field programmable gate arrays
Filters
Hardware
Machine vision
Navigation
Robot vision systems
ISSN:1946-147X
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Abstract Convolutional networks (ConvNets) are biologically inspired hierarchical architectures that can be trained to perform a variety of detection, recognition and segmentation tasks. ConvNets have a feed-forward architecture consisting of multiple linear convolution filters interspersed with pointwise non-linear squashing functions. This paper presents an efficient implementation of ConvNets on a low-end DSP-oriented field programmable gate array (FPGA). The implementation exploits the inherent parallelism of ConvNets and takes full advantage of multiple hardware multiply accumulate units on the FPGA. The entire system uses a single FPGA with an external memory module, and no extra parts. A network compiler software was implemented, which takes a description of a trained ConvNet and compiles it into a sequence of instructions for the ConvNet Processor (CNP). A ConvNet face detection system was implemented and tested. Face detection on a 512 times 384 frame takes 100 ms (10 frames per second), which corresponds to an average performance of 3.4 times 10 9 connections per second for this 340 million connection network. The design can be used for low-power, lightweight embedded vision systems for micro-UAVs and other small robots.
AbstractList Convolutional networks (ConvNets) are biologically inspired hierarchical architectures that can be trained to perform a variety of detection, recognition and segmentation tasks. ConvNets have a feed-forward architecture consisting of multiple linear convolution filters interspersed with pointwise non-linear squashing functions. This paper presents an efficient implementation of ConvNets on a low-end DSP-oriented field programmable gate array (FPGA). The implementation exploits the inherent parallelism of ConvNets and takes full advantage of multiple hardware multiply accumulate units on the FPGA. The entire system uses a single FPGA with an external memory module, and no extra parts. A network compiler software was implemented, which takes a description of a trained ConvNet and compiles it into a sequence of instructions for the ConvNet Processor (CNP). A ConvNet face detection system was implemented and tested. Face detection on a 512 times 384 frame takes 100 ms (10 frames per second), which corresponds to an average performance of 3.4 times 10 9 connections per second for this 340 million connection network. The design can be used for low-power, lightweight embedded vision systems for micro-UAVs and other small robots.
Author Han, J.Y.
Farabet, C.
Poulet, C.
LeCun, Y.
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  givenname: C.
  surname: Farabet
  fullname: Farabet, C.
  organization: Courant Inst. of Math. Sci., New York Univ., New York, NY, USA
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  organization: Perceptive Pixel Inc., New York, NY, USA
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  surname: LeCun
  fullname: LeCun, Y.
  organization: Courant Inst. of Math. Sci., New York Univ., New York, NY, USA
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Snippet Convolutional networks (ConvNets) are biologically inspired hierarchical architectures that can be trained to perform a variety of detection, recognition and...
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StartPage 32
SubjectTerms Cameras
Convolution
Face detection
Feedforward systems
Field programmable gate arrays
Filters
Hardware
Machine vision
Navigation
Robot vision systems
Title CNP: An FPGA-based processor for Convolutional Networks
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