Exploiting symmetry in SAT-based boolean matching for heterogeneous FPGA technology mapping

The Boolean matching problem is a key procedure in technology mapping for heterogeneous field programmable gate arrays (FPGA), and SAT-based Boolean matching (SAT-BM) provides a highly flexible solution for various FPGA architectures. However, the computational complexity of state-of-the-art SAT-BM...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:2007 IEEE/ACM International Conference on Computer-Aided Design s. 350 - 353
Hlavní autoři: Yu Hu, Shih, V., Majumdar, R., Lei He
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.11.2007
Témata:
Circuits
Computational complexity
Computer architecture
Encoding
Field programmable gate arrays
Logic devices
Programmable logic arrays
Runtime
Space technology
Table lookup
ISBN:1424413818, 9781424413812
ISSN:1092-3152
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Popis
Shrnutí:The Boolean matching problem is a key procedure in technology mapping for heterogeneous field programmable gate arrays (FPGA), and SAT-based Boolean matching (SAT-BM) provides a highly flexible solution for various FPGA architectures. However, the computational complexity of state-of-the-art SAT-BM prohibits its application practically. In this paper we propose an efficient SAT-BM algorithm by exploring function and architectural symmetries. While the most recent work obtained up to 13times speedup, we achieve up to 200times speedup, when both are compared to the original SAT-BM algorithm.
ISBN:1424413818
9781424413812
ISSN:1092-3152
DOI:10.1109/ICCAD.2007.4397289