Exploiting symmetry in SAT-based boolean matching for heterogeneous FPGA technology mapping

The Boolean matching problem is a key procedure in technology mapping for heterogeneous field programmable gate arrays (FPGA), and SAT-based Boolean matching (SAT-BM) provides a highly flexible solution for various FPGA architectures. However, the computational complexity of state-of-the-art SAT-BM...

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Vydané v:	2007 IEEE/ACM International Conference on Computer-Aided Design s. 350 - 353
Hlavní autori:	Yu Hu, Shih, V., Majumdar, R., Lei He
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 01.11.2007
Predmet:	Circuits Computational complexity Computer architecture Encoding Field programmable gate arrays Logic devices Programmable logic arrays Runtime Space technology Table lookup
ISBN:	1424413818, 9781424413812
ISSN:	1092-3152
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