Exploiting symmetry in SAT-based boolean matching for heterogeneous FPGA technology mapping
The Boolean matching problem is a key procedure in technology mapping for heterogeneous field programmable gate arrays (FPGA), and SAT-based Boolean matching (SAT-BM) provides a highly flexible solution for various FPGA architectures. However, the computational complexity of state-of-the-art SAT-BM...
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| Vydáno v: | 2007 IEEE/ACM International Conference on Computer-Aided Design s. 350 - 353 |
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| Jazyk: | angličtina |
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IEEE
01.11.2007
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| ISBN: | 1424413818, 9781424413812 |
| ISSN: | 1092-3152 |
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| Abstract | The Boolean matching problem is a key procedure in technology mapping for heterogeneous field programmable gate arrays (FPGA), and SAT-based Boolean matching (SAT-BM) provides a highly flexible solution for various FPGA architectures. However, the computational complexity of state-of-the-art SAT-BM prohibits its application practically. In this paper we propose an efficient SAT-BM algorithm by exploring function and architectural symmetries. While the most recent work obtained up to 13times speedup, we achieve up to 200times speedup, when both are compared to the original SAT-BM algorithm. |
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| AbstractList | The Boolean matching problem is a key procedure in technology mapping for heterogeneous field programmable gate arrays (FPGA), and SAT-based Boolean matching (SAT-BM) provides a highly flexible solution for various FPGA architectures. However, the computational complexity of state-of-the-art SAT-BM prohibits its application practically. In this paper we propose an efficient SAT-BM algorithm by exploring function and architectural symmetries. While the most recent work obtained up to 13times speedup, we achieve up to 200times speedup, when both are compared to the original SAT-BM algorithm. |
| Author | Majumdar, R. Lei He Yu Hu Shih, V. |
| Author_xml | – sequence: 1 surname: Yu Hu fullname: Yu Hu organization: Univ. of California, Los Angeles – sequence: 2 givenname: V. surname: Shih fullname: Shih, V. – sequence: 3 givenname: R. surname: Majumdar fullname: Majumdar, R. – sequence: 4 surname: Lei He fullname: Lei He organization: Univ. of California, Los Angeles |
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| Snippet | The Boolean matching problem is a key procedure in technology mapping for heterogeneous field programmable gate arrays (FPGA), and SAT-based Boolean matching... |
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| StartPage | 350 |
| SubjectTerms | Circuits Computational complexity Computer architecture Encoding Field programmable gate arrays Logic devices Programmable logic arrays Runtime Space technology Table lookup |
| Title | Exploiting symmetry in SAT-based boolean matching for heterogeneous FPGA technology mapping |
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