Exploiting symmetry in SAT-based boolean matching for heterogeneous FPGA technology mapping

The Boolean matching problem is a key procedure in technology mapping for heterogeneous field programmable gate arrays (FPGA), and SAT-based Boolean matching (SAT-BM) provides a highly flexible solution for various FPGA architectures. However, the computational complexity of state-of-the-art SAT-BM...

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Published in:2007 IEEE/ACM International Conference on Computer-Aided Design pp. 350 - 353
Main Authors: Yu Hu, Shih, V., Majumdar, R., Lei He
Format: Conference Proceeding
Language:English
Published: IEEE 01.11.2007
Subjects:
Circuits
Computational complexity
Computer architecture
Encoding
Field programmable gate arrays
Logic devices
Programmable logic arrays
Runtime
Space technology
Table lookup
ISBN:1424413818, 9781424413812
ISSN:1092-3152
Online Access:Get full text
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Abstract The Boolean matching problem is a key procedure in technology mapping for heterogeneous field programmable gate arrays (FPGA), and SAT-based Boolean matching (SAT-BM) provides a highly flexible solution for various FPGA architectures. However, the computational complexity of state-of-the-art SAT-BM prohibits its application practically. In this paper we propose an efficient SAT-BM algorithm by exploring function and architectural symmetries. While the most recent work obtained up to 13times speedup, we achieve up to 200times speedup, when both are compared to the original SAT-BM algorithm.
AbstractList The Boolean matching problem is a key procedure in technology mapping for heterogeneous field programmable gate arrays (FPGA), and SAT-based Boolean matching (SAT-BM) provides a highly flexible solution for various FPGA architectures. However, the computational complexity of state-of-the-art SAT-BM prohibits its application practically. In this paper we propose an efficient SAT-BM algorithm by exploring function and architectural symmetries. While the most recent work obtained up to 13times speedup, we achieve up to 200times speedup, when both are compared to the original SAT-BM algorithm.
Author Majumdar, R.
Lei He
Yu Hu
Shih, V.
Author_xml – sequence: 1
  surname: Yu Hu
  fullname: Yu Hu
  organization: Univ. of California, Los Angeles
– sequence: 2
  givenname: V.
  surname: Shih
  fullname: Shih, V.
– sequence: 3
  givenname: R.
  surname: Majumdar
  fullname: Majumdar, R.
– sequence: 4
  surname: Lei He
  fullname: Lei He
  organization: Univ. of California, Los Angeles
BookMark eNo10M1Kw0AUBeARK1hrX0A38wKp85vJLENsa6GgYF25KJOZm3YgmQlJBPP2Rqyry4HvnMW9Q7MQAyD0QMmKUqKfdkWRP68YIWoluFYs01doqVVGBROC8ozpa3T3H2g2Q_OpxRJOJbtFy773JeFSSsJJOkef6--2jn7w4YT7sWlg6EbsA37PD0lpenC4jLEGE3BjBnv-ZVXs8BkG6OIJAsSvHm_etjkewJ5DrONpnGjbTvIe3VSm7mF5uQv0sVkfipdk_7rdFfk-8UzQISmJVBWUaWpSoNKCKbVSwhpnnZYA1nDtuCWOpqQColIB0tEKFHV2YkD4Aj3-7XoAOLadb0w3Hi-_4T_Rhlno
ContentType Conference Proceeding
DBID 6IE
6IH
CBEJK
RIE
RIO
DOI 10.1109/ICCAD.2007.4397289
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan (POP) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP) 1998-present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EISBN 9781424413829
1424413826
EndPage 353
ExternalDocumentID 4397289
Genre orig-research
GroupedDBID 123
6IE
6IF
6IH
6IL
6IN
AAWTH
ABLEC
ADZIZ
ALMA_UNASSIGNED_HOLDINGS
APO
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
CHZPO
FEDTE
IEGSK
IJVOP
M43
OCL
RIE
RIL
RIO
ID FETCH-LOGICAL-i241t-b057feb66a6e15ceab9774cadcd95eeca39d3c0d160fe0764e5d1fe71dc74ce03
IEDL.DBID RIE
ISBN 1424413818
9781424413812
ISICitedReferencesCount 13
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000253303700055&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
ISSN 1092-3152
IngestDate Wed Aug 27 02:20:43 EDT 2025
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i241t-b057feb66a6e15ceab9774cadcd95eeca39d3c0d160fe0764e5d1fe71dc74ce03
PageCount 4
ParticipantIDs ieee_primary_4397289
PublicationCentury 2000
PublicationDate 2007-11
PublicationDateYYYYMMDD 2007-11-01
PublicationDate_xml – month: 11
  year: 2007
  text: 2007-11
PublicationDecade 2000
PublicationTitle 2007 IEEE/ACM International Conference on Computer-Aided Design
PublicationTitleAbbrev ICCAD
PublicationYear 2007
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssib035550306
ssj0020286
ssj0000668987
Score 1.57597
Snippet The Boolean matching problem is a key procedure in technology mapping for heterogeneous field programmable gate arrays (FPGA), and SAT-based Boolean matching...
SourceID ieee
SourceType Publisher
StartPage 350
SubjectTerms Circuits
Computational complexity
Computer architecture
Encoding
Field programmable gate arrays
Logic devices
Programmable logic arrays
Runtime
Space technology
Table lookup
Title Exploiting symmetry in SAT-based boolean matching for heterogeneous FPGA technology mapping
URI https://ieeexplore.ieee.org/document/4397289
WOSCitedRecordID wos000253303700055&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PS8MwGA1zeNCLPzbxNzl4tK5Zl3Q5juFUkDFwysDDSJOvWnCtbJ2w_94vWdspePHWlkBp-Mh7-freCyFXPNLaxCK25hjtdVSkPBsB4uGyYDhTfqCcQPblMRwOu5OJHNXIdeWFAQAnPoMbe-n-5ZtML22rrGXBEzcIW2QrDMXaq1XWDsImt_S36q8glHZld7P5Qhx1TiNf2pA-3i5NXsxCVpn9VNy3S3eNL1sPfZySddRh8fpf57A4GBrs_e8D9klz4-ejowqpDkgN0kOy-yOKsEFenRgvsSJouljNZpDPVzRJ6VNv7FmkMxTp-AeolCLFdfpLinSXvls1TYZFCNlyQQejux7Nq2Y9DrXpD29N8jy4HffvveLgBS9BQM-9CElcDJEQSgDjGlRkWaJWRhvJAbQKpAm0b5jwY_BD0QFuWAwhMxqHgR8ckXqapXBMqGAmsMqUQHDVkdBGdmACFiEKGhOEMj4hDTtN0891tsa0mKHTvx-fkR3XW3VewHNSz-dLuCDb-itPFvNLVxDfzSuwBw
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PT8IwGG0QTdSLP8D42x48Olm3tWNHQkSISEhEQ-KBdO03XSKbgWHCf29btqGJF2_b0sPWfOl7_fbeK0LXNBRCRizS5hhheTzklo4AsdSyICnhtsuNQPal7w8GzfE4GFbQTemFAQAjPoNbfWn-5ctULHSrrKHBU20QNtAm9TzHXrm1iupRwEk1AS47LApMm0Fzvf1SSGq8RnagY_qoU9i8iAatIv0pv3cKf40dNHptNSmrsMP8BX6dxGKAqLP3v0_YR_W1ow8PS6w6QBVIDtHujzDCGno1crxYy6DxfDmdQjZb4jjBT62RpbFOYkXIP4AnWJFco8DEivDid62nSVUZQrqY487wvoWzsl2vhur8h7c6eu7cjdpdKz96wYoVpGdWqGhcBCFjnAGhAnioeaLgUsiAAgjuBtIVtiTMjsD2mQdUkgh8IoUaBrZ7hKpJmsAxwoxIV2tTXEa5F4Cj-IF0SahwUErXD6ITVNPTNPlcpWtM8hk6_fvxFdrujh77k35v8HCGdkyn1TgDz1E1my3gAm2Jryyezy5NcXwDKaKzTg
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2007+IEEE%2FACM+International+Conference+on+Computer-Aided+Design&rft.atitle=Exploiting+symmetry+in+SAT-based+boolean+matching+for+heterogeneous+FPGA+technology+mapping&rft.au=Yu+Hu&rft.au=Shih%2C+V.&rft.au=Majumdar%2C+R.&rft.au=Lei+He&rft.date=2007-11-01&rft.pub=IEEE&rft.isbn=9781424413812&rft.issn=1092-3152&rft.spage=350&rft.epage=353&rft_id=info:doi/10.1109%2FICCAD.2007.4397289&rft.externalDocID=4397289
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1092-3152&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1092-3152&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1092-3152&client=summon