Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

An SR-latch can be regarded as primitive to build a True Random Number Generation (TRNG) or Physically Unclonable Function (PUF). Indeed, when the SR inputs of the latch are tied together and go from an unknown state (i.e. S=R=1) to a memory state (i.e. S=R=0), the behaviour depends on the balance b...

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Bibliographic Details

Published in:	2018 21st Euromicro Conference on Digital System Design (DSD) pp. 508 - 515
Main Authors:	Danger, Jean-Luc, Yashiro, Risa, Graba, Tarik, Mathieu, Yves, Si-Merabet, Abdelmalek, Sakiyama, Kazuo, Miura, Noriyuki, Nagata, Makoto
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.08.2018
Subjects:	analysis Cryptography Delays Entropy FD SOI Latches Logic gates PUF Reliability Transistors TRNG
Online Access:	Get full text
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