Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology
An SR-latch can be regarded as primitive to build a True Random Number Generation (TRNG) or Physically Unclonable Function (PUF). Indeed, when the SR inputs of the latch are tied together and go from an unknown state (i.e. S=R=1) to a memory state (i.e. S=R=0), the behaviour depends on the balance b...
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| Vydané v: | 2018 21st Euromicro Conference on Digital System Design (DSD) s. 508 - 515 |
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| Hlavní autori: | , , , , , , , |
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01.08.2018
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| Abstract | An SR-latch can be regarded as primitive to build a True Random Number Generation (TRNG) or Physically Unclonable Function (PUF). Indeed, when the SR inputs of the latch are tied together and go from an unknown state (i.e. S=R=1) to a memory state (i.e. S=R=0), the behaviour depends on the balance between the NAND or NOR gates composing the latch. With the process mismatch, there is a great chance that the latch converges towards the same state, thus creating a PUF equivalent to a SRAM-PUF or latch-PUF. However, if the latch is well-balanced, it can enter a metastable state and converges to a stable state depending on the input noise, thus making a TRNG. In order to make sure some latches are able to behave like a TRNG, and some like a PUF, we consider a set of latches driven by the same SR signal. A test-chip in 28nm UTBB-FDSOI technology has been designed with 1024 latches in order to analyze the behavior. The FD-SOI technology enables easy change of the performances of gates using the body biasing, which consists in applying a specific body voltage to each gate. Hence, the two NOR gates composing the SR-latch can be tuned individually to get the optimality, i.e. the maximum entropy, for both PUF and TRNG. The results show that the optimal point is the same for both PUF and TRNG, and that the proposed structure can generate concurrently a PUF with high reliability, and a TRNG with high speed. |
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| AbstractList | An SR-latch can be regarded as primitive to build a True Random Number Generation (TRNG) or Physically Unclonable Function (PUF). Indeed, when the SR inputs of the latch are tied together and go from an unknown state (i.e. S=R=1) to a memory state (i.e. S=R=0), the behaviour depends on the balance between the NAND or NOR gates composing the latch. With the process mismatch, there is a great chance that the latch converges towards the same state, thus creating a PUF equivalent to a SRAM-PUF or latch-PUF. However, if the latch is well-balanced, it can enter a metastable state and converges to a stable state depending on the input noise, thus making a TRNG. In order to make sure some latches are able to behave like a TRNG, and some like a PUF, we consider a set of latches driven by the same SR signal. A test-chip in 28nm UTBB-FDSOI technology has been designed with 1024 latches in order to analyze the behavior. The FD-SOI technology enables easy change of the performances of gates using the body biasing, which consists in applying a specific body voltage to each gate. Hence, the two NOR gates composing the SR-latch can be tuned individually to get the optimality, i.e. the maximum entropy, for both PUF and TRNG. The results show that the optimal point is the same for both PUF and TRNG, and that the proposed structure can generate concurrently a PUF with high reliability, and a TRNG with high speed. |
| Author | Si-Merabet, Abdelmalek Graba, Tarik Mathieu, Yves Sakiyama, Kazuo Nagata, Makoto Danger, Jean-Luc Yashiro, Risa Miura, Noriyuki |
| Author_xml | – sequence: 1 givenname: Jean-Luc surname: Danger fullname: Danger, Jean-Luc – sequence: 2 givenname: Risa surname: Yashiro fullname: Yashiro, Risa – sequence: 3 givenname: Tarik surname: Graba fullname: Graba, Tarik – sequence: 4 givenname: Yves surname: Mathieu fullname: Mathieu, Yves – sequence: 5 givenname: Abdelmalek surname: Si-Merabet fullname: Si-Merabet, Abdelmalek – sequence: 6 givenname: Kazuo surname: Sakiyama fullname: Sakiyama, Kazuo – sequence: 7 givenname: Noriyuki surname: Miura fullname: Miura, Noriyuki – sequence: 8 givenname: Makoto surname: Nagata fullname: Nagata, Makoto |
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| Snippet | An SR-latch can be regarded as primitive to build a True Random Number Generation (TRNG) or Physically Unclonable Function (PUF). Indeed, when the SR inputs of... |
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| StartPage | 508 |
| SubjectTerms | analysis Cryptography Delays Entropy FD SOI Latches Logic gates PUF Reliability Transistors TRNG |
| Title | Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology |
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