Ma, Y., Cao, Y., Vrudhula, S., & Seo, J. (2017, September). An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. International Conference on Field-programmable Logic and Applications, 1-8. https://doi.org/10.23919/FPL.2017.8056824
Citace podle Chicago (17th ed.)Ma, Yufei, Yu Cao, Sarma Vrudhula, a Jae-sun Seo. "An Automatic RTL Compiler for High-throughput FPGA Implementation of Diverse Deep Convolutional Neural Networks." International Conference on Field-programmable Logic and Applications Sep. 2017: 1-8. https://doi.org/10.23919/FPL.2017.8056824.
Citace podle MLA (9th ed.)Ma, Yufei, et al. "An Automatic RTL Compiler for High-throughput FPGA Implementation of Diverse Deep Convolutional Neural Networks." International Conference on Field-programmable Logic and Applications, Sep. 2017, pp. 1-8, https://doi.org/10.23919/FPL.2017.8056824.