An Analysis and a Solution of False Conflicts for Hardware Transactional Memory

Transactional memory is a promising paradigm for shared-memory parallel programming model. On TMs, transactions are executed speculatively in parallel as long as any access conflict is not detected. On general hardware transactional memories (HTMs), conflicts degrade the performance because of the o...

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Veröffentlicht in:2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) S. 529 - 532
Hauptverfasser: Futamase, Yuki, Hayashi, Masaki, Tajimi, Tomoki, Shioya, Ryota, Goshima, Masahiro, Tsumura, Tomoaki
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.12.2018
Schlagworte:
Encoding
Hardware
Memory management
Message systems
Parallel processing
Parallel programming
Synchronization
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Zusammenfassung:Transactional memory is a promising paradigm for shared-memory parallel programming model. On TMs, transactions are executed speculatively in parallel as long as any access conflict is not detected. On general hardware transactional memories (HTMs), conflicts degrade the performance because of the overhead for retrying transactions, and it is important to avoid conflicts. HTM generally detects access conflicts on cache-line granularity, and this causes accesses on different variables that are on a cache line to be falsely detected as conflicting accesses. In this paper, we analyze how frequently such false conflicts occur and what type of coding can cause them. As a result of the analysis, we confirmed that the false conflicts account for 27.4% on average and even 99.9% at a maximum of all detected conflicts. We also propose a light-weight fine-grained conflict detection mechanism and show that it can reduce the execution cycles by 17.7% on average and 36.5% at a maximum.
DOI:10.1109/ICECS.2018.8617977