A Sparse Direct Solver for Distributed Memory Xeon Phi-Accelerated Systems

This paper presents the first sparse direct solver for distributed memory systems comprising hybrid multicourse CPU and Intel Xeon Pico-processors. It builds on the algorithmic approach of SuperLU_DIST, which is right-looking and statically pivoted. Our contribution is a novel algorithm, called the...

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Bibliographic Details
Published in:Proceedings - IEEE International Parallel and Distributed Processing Symposium pp. 71 - 81
Main Authors: Sao, Piyush, Xing Liu, Vuduc, Richard, Xiaoye Li
Format: Conference Proceeding
Language:English
Published: IEEE 01.05.2015
Subjects:
Acceleration
Communication-avoiding algorithm
GPU
Graphics processing units
Heterogeneous computing
Memory management
Microwave integrated circuits
MPI
Multicore processing
OpenMP
Parallel processing
Sparse Direct Solver
Sparse matrices
Xeon-Phi acceleration
ISSN:1530-2075
Online Access:Get full text
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Summary:This paper presents the first sparse direct solver for distributed memory systems comprising hybrid multicourse CPU and Intel Xeon Pico-processors. It builds on the algorithmic approach of SuperLU_DIST, which is right-looking and statically pivoted. Our contribution is a novel algorithm, called the HALO. The name is shorthand for highly asynchronous lazy offload, it refers tithe way the algorithm combines highly aggressive use of asynchrony with accelerated offload, lazy updates, and data shadowing (a la halo or ghost zones), all of which serve to hide and reduce communication, whether to local memory, across the network, or over PCIe. We further augment HALO with a model-driven autotuning heuristicthat chooses the intra-node division of labor among CPU and Xeon Pico-processor components. When integrated into SuperLU_DIST and evaluated on a variety of realistic test problems in both single-node and multi-node configurations, the resulting implementation achieves speedups of unto 2.5× over an already efficient multicourse CPU implementation, and achieves up to 83% of a machine-specific upper-bound that we haveestimated. Our analysis quantifies how well our implementation performs and allows us to speculate on the potential speedups that might come from variety of future improvements to the algorithm and system.
ISSN:1530-2075
DOI:10.1109/IPDPS.2015.104