System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments

In particle physics experiments, the momenta of charged particles are studied by observing their deflection in a magnetic field. Dedicated detectors measure the particle tracks and complex algorithms are required for track recognition and reconstruction. This CPU-intensive task is usually implemente...

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Vydáno v:DSD 2008 : 11th Euromicro Conference on Digital System Design Architectures, Methods, and Tools : proceedings, September 3-5, 2008, Parma, Italy s. 599 - 605
Hlavní autoři: Ming Liu, Kuehn, W., Zhonghai Lu, Jantsch, A.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.09.2008
Témata:
Clustering algorithms
Detectors
Field programmable gate arrays
FPGA implementation
Magnetic field measurement
Particle measurements
particle physics
particle track reconstruction
Particle tracking
pattern recognition
Physics
Real time systems
Software algorithms
System-on-a-chip
System-on-Chip application
ISBN:9780769532776, 0769532772
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Shrnutí:In particle physics experiments, the momenta of charged particles are studied by observing their deflection in a magnetic field. Dedicated detectors measure the particle tracks and complex algorithms are required for track recognition and reconstruction. This CPU-intensive task is usually implemented as off-line software running on PC clusters. In this paper, we present a system-on-chip design for the track recognition and reconstruction based on modern FPGA technologies. The basic principle of the algorithm is ported from software into the FPGA fabric. The fundamental architecture of the tracking processor is described in detail. Working as processing engines in compute nodes, the tracking processor contributes to recognize potential track candidates in real-time and promotes the selection efficiency of the data acquisition and trigger system. Our design study shows that the tracking module can be integrated in a single Xilinx Virtex-4 FX60 FPGA. The processing capability of the design is about 16.7K sub-events per second per module with our experimental setup, which achieves 20 times speedup compared to the software implementation.
ISBN:9780769532776
0769532772
DOI:10.1109/DSD.2008.97