FPGA implementation of modular architecture for packet classification using field split algorithm

Packet classification has proved to be an important challenge in network processing. It requires comparing each packet with rules and forwarding the packet according to the highest priority matching rule. The criteria are comprised of a set of rules that specify the content of specific packet header...

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Published in:2015 International Conference on Communications and Signal Processing (ICCSP) pp. 1098 - 1101
Main Authors: Meshram, Mangesh, Kakde, Sandeep, Suryawanshi, Yogesh, Deodhe, Yeshwant
Format: Conference Proceeding
Language:English
Published: IEEE 01.04.2015
Subjects:
5-tuple
Bit Vector Algorithm
Classification algorithms
Field Split Bit Vector Algorithm
Hardware
Latency
Logic gates
Packet Classification
Quality of service
Quality of Services
Table lookup
Throughput
Yttrium
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Abstract Packet classification has proved to be an important challenge in network processing. It requires comparing each packet with rules and forwarding the packet according to the highest priority matching rule. The criteria are comprised of a set of rules that specify the content of specific packet header fields to either software or hardware. Packet classification is widely used as a core function for various applications in networking. So increase demands in throughput and reduce latency. Also the performance of today's packet classification solutions depends on the rule sets. In this paper, we propose a modular Bit-Vector (BV) based architecture to perform high-speed packet classification on Field Programmable Gate Array (FPGA) Matching packets with some predefined rules using XillinxISE13.2 software.
AbstractList Packet classification has proved to be an important challenge in network processing. It requires comparing each packet with rules and forwarding the packet according to the highest priority matching rule. The criteria are comprised of a set of rules that specify the content of specific packet header fields to either software or hardware. Packet classification is widely used as a core function for various applications in networking. So increase demands in throughput and reduce latency. Also the performance of today's packet classification solutions depends on the rule sets. In this paper, we propose a modular Bit-Vector (BV) based architecture to perform high-speed packet classification on Field Programmable Gate Array (FPGA) Matching packets with some predefined rules using XillinxISE13.2 software.
Author Deodhe, Yeshwant
Kakde, Sandeep
Meshram, Mangesh
Suryawanshi, Yogesh
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Snippet Packet classification has proved to be an important challenge in network processing. It requires comparing each packet with rules and forwarding the packet...
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StartPage 1098
SubjectTerms 5-tuple
Bit Vector Algorithm
Classification algorithms
Field Split Bit Vector Algorithm
Hardware
Latency
Logic gates
Packet Classification
Quality of service
Quality of Services
Table lookup
Throughput
Yttrium
Title FPGA implementation of modular architecture for packet classification using field split algorithm
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