Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation

Householder Transformation (HT) is a prime building block of widely used numerical linear algebra primitives such as QR factorization. Despite years of intense research on HT, there exists a scope to expose higher Instruction Level Parallelism in HT through algorithmic transforms. In this paper, we...

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Vydáno v:2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) s. 98 - 103
Hlavní autoři: Merchant, Farhad, Vatwani, Tarun, Chattopadhyay, Anupam, Raha, Soumyendu, Nandy, S. K., Narayan, Ranjani
Médium: Konferenční příspěvek Journal Article
Jazyk:angličtina
Vydáno: IEEE 01.01.2016
Témata:
Algorithm design and analysis
Algorithms
Co-design
computation
Computer architecture
Conferences
Exposure
Factorization
Heat treatment
Householder transformations
Linear algebra
numerical linear algebra
Optimization
Parallel processing
parallelism
reconfigurable architectures
Software algorithms
Transformations (mathematics)
Transforms
ISSN:2380-6923
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Abstract Householder Transformation (HT) is a prime building block of widely used numerical linear algebra primitives such as QR factorization. Despite years of intense research on HT, there exists a scope to expose higher Instruction Level Parallelism in HT through algorithmic transforms. In this paper, we propose several novel algorithmic transformations in HT to expose higher Instruction-Level Parallelism. Our propositions are backed by theoretical proofs and a series of experiments using commercial general-purpose processors. Finally, we show that algorithm-architecture co-design leads to the most efficient realization of HT. A detailed experimental study with architectural modifications is presented for a commercial CGRA. The benchmarking results with some of the recent HT implementations show 30-40% improvement in performance.
AbstractList Householder Transformation (HT) is a prime building block of widely used numerical linear algebra primitives such as QR factorization. Despite years of intense research on HT, there exists a scope to expose higher Instruction Level Parallelism in HT through algorithmic transforms. In this paper, we propose several novel algorithmic transformations in HT to expose higher Instruction-Level Parallelism. Our propositions are backed by theoretical proofs and a series of experiments using commercial general-purpose processors. Finally, we show that algorithm-architecture co-design leads to the most efficient realization of HT. A detailed experimental study with architectural modifications is presented for a commercial CGRA. The benchmarking results with some of the recent HT implementations show 30-40% improvement in performance.
Author Nandy, S. K.
Narayan, Ranjani
Vatwani, Tarun
Chattopadhyay, Anupam
Merchant, Farhad
Raha, Soumyendu
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  surname: Chattopadhyay
  fullname: Chattopadhyay, Anupam
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  givenname: Soumyendu
  surname: Raha
  fullname: Raha, Soumyendu
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  givenname: S. K.
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  organization: CADLab, Indian Inst. of Sci., Bangalore, India
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  givenname: Ranjani
  surname: Narayan
  fullname: Narayan, Ranjani
  email: ranjani.narayan@morphingmachines.com
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Snippet Householder Transformation (HT) is a prime building block of widely used numerical linear algebra primitives such as QR factorization. Despite years of intense...
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StartPage 98
SubjectTerms Algorithm design and analysis
Algorithms
Co-design
computation
Computer architecture
Conferences
Exposure
Factorization
Heat treatment
Householder transformations
Linear algebra
numerical linear algebra
Optimization
Parallel processing
parallelism
reconfigurable architectures
Software algorithms
Transformations (mathematics)
Transforms
Title Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation
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