Synthesis and Simulation of FPGA Based Hardware Design of RC4 Stream Cipher

This paper is focused on the synthesis and simulation of RC4 algorithm, which can be implemented on FPGA. A variable length key from 1 to 16 bytes is used by RC4 algorithm to initialize a 256-byte array. The subsequent pseudo-random bytes are generated by using this 256-byte array which is then gene...

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Vydáno v:Proceedings (International Confernce on Computational Intelligence and Communication Networks) s. 1177 - 1182
Hlavní autoři: Sonawane, Pradeep J., Bhadade, Umesh S.
Médium: Konferenční příspěvek Journal Article
Jazyk:angličtina
Vydáno: IEEE 01.12.2015
Témata:
Algorithms
Arrays
Ciphers
Ciphertext
Computer simulation
Encryption
Field programmable gate arrays
Generators
Hardware
key scheduling algorithm
plaintext
pseudorandom number generation
Software
Software algorithms
Synthesis
Texts
ISSN:2472-7555
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Shrnutí:This paper is focused on the synthesis and simulation of RC4 algorithm, which can be implemented on FPGA. A variable length key from 1 to 16 bytes is used by RC4 algorithm to initialize a 256-byte array. The subsequent pseudo-random bytes are generated by using this 256-byte array which is then generates a pseudorandom stream, which is EX-ORed with the plaintext/cipher text to give the cipher text/plaintext. The RC4 stream cipher has two phases which are key scheduling algorithm (KSA) phase and the pseudorandom generation algorithm (PRGA) phase. For every new key both phases must be performed. The RC4 is very successful algorithm in the field of cryptography because of its speed and simplicity and it is very easy to develop this algorithm in both software and hardware. The RC4 code is written in verilog language and based on synthesis result it can be further downloaded on FPGA for its hardware realization.
Bibliografie:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Conference-1
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SourceType-Conference Papers & Proceedings-2
ISSN:2472-7555
DOI:10.1109/CICN.2015.228