Synthesis and Simulation of FPGA Based Hardware Design of RC4 Stream Cipher
This paper is focused on the synthesis and simulation of RC4 algorithm, which can be implemented on FPGA. A variable length key from 1 to 16 bytes is used by RC4 algorithm to initialize a 256-byte array. The subsequent pseudo-random bytes are generated by using this 256-byte array which is then gene...
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| Vydáno v: | Proceedings (International Confernce on Computational Intelligence and Communication Networks) s. 1177 - 1182 |
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| Jazyk: | angličtina |
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01.12.2015
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| ISSN: | 2472-7555 |
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| Abstract | This paper is focused on the synthesis and simulation of RC4 algorithm, which can be implemented on FPGA. A variable length key from 1 to 16 bytes is used by RC4 algorithm to initialize a 256-byte array. The subsequent pseudo-random bytes are generated by using this 256-byte array which is then generates a pseudorandom stream, which is EX-ORed with the plaintext/cipher text to give the cipher text/plaintext. The RC4 stream cipher has two phases which are key scheduling algorithm (KSA) phase and the pseudorandom generation algorithm (PRGA) phase. For every new key both phases must be performed. The RC4 is very successful algorithm in the field of cryptography because of its speed and simplicity and it is very easy to develop this algorithm in both software and hardware. The RC4 code is written in verilog language and based on synthesis result it can be further downloaded on FPGA for its hardware realization. |
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| AbstractList | This paper is focused on the synthesis and simulation of RC4 algorithm, which can be implemented on FPGA. A variable length key from 1 to 16 bytes is used by RC4 algorithm to initialize a 256-byte array. The subsequent pseudo-random bytes are generated by using this 256-byte array which is then generates a pseudorandom stream, which is EX-ORed with the plaintext/cipher text to give the cipher text/plaintext. The RC4 stream cipher has two phases which are key scheduling algorithm (KSA) phase and the pseudorandom generation algorithm (PRGA) phase. For every new key both phases must be performed. The RC4 is very successful algorithm in the field of cryptography because of its speed and simplicity and it is very easy to develop this algorithm in both software and hardware. The RC4 code is written in verilog language and based on synthesis result it can be further downloaded on FPGA for its hardware realization. |
| Author | Sonawane, Pradeep J. Bhadade, Umesh S. |
| Author_xml | – sequence: 1 givenname: Pradeep J. surname: Sonawane fullname: Sonawane, Pradeep J. email: prijesh.s87@gmail.com organization: Electron. & Telecommun. Dept., S.S.B.T.'s COET, Bambhori, India – sequence: 2 givenname: Umesh S. surname: Bhadade fullname: Bhadade, Umesh S. email: umeshbhadade@rediffmail.com organization: Electron. & Telecommun. Dept., S.S.B.T.'s COET, Bambhori, India |
| BookMark | eNotjDtPwzAURg0CibZ0ZGLxyJJy7cSvsQT6EBUgCnN029xQozxKnAr13xMB0yed7-gM2Vnd1MTYlYCJEOBu02X6NJEg1ERKe8KGQoEDAKPjUzaQiZGRUUpdsHEInz0XWihr5IA9ro91t6PgA8c652tfHUrsfFPzpuCzl_mU32GgnC-wzb-xJX7fux-_72ua8HXXElY89fsdtZfsvMAy0Ph_R-x99vCWLqLV83yZTleRl2C7KAHjCEBD4YQjqxRsFErcgMM8TkyORhXS5gikNMKWlHRiq7BwxlkJehOP2M1fd982XwcKXVb5sKWyxJqaQ8iEjZXWSd_q1es_1RNRtm99he0xMyrR0sr4B23zWec |
| CODEN | IEEPAD |
| ContentType | Conference Proceeding Journal Article |
| DBID | 6IE 6IL CBEJK RIE RIL 7SC 8FD JQ2 L7M L~C L~D |
| DOI | 10.1109/CICN.2015.228 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP All) 1998-Present Computer and Information Systems Abstracts Technology Research Database ProQuest Computer Science Collection Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Academic Computer and Information Systems Abstracts Professional |
| DatabaseTitle | Computer and Information Systems Abstracts Technology Research Database Computer and Information Systems Abstracts – Academic Advanced Technologies Database with Aerospace ProQuest Computer Science Collection Computer and Information Systems Abstracts Professional |
| DatabaseTitleList | Computer and Information Systems Abstracts |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Xplore url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Computer Science |
| EISBN | 1509000763 9781509000760 |
| EISSN | 2472-7555 |
| EndPage | 1182 |
| ExternalDocumentID | 7546282 |
| Genre | orig-research |
| GroupedDBID | 6IE 6IF 6IH 6IK 6IL 6IN AAJGR AAWTH ABLEC ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO IEGSK IPLJI M43 OCL RIE RIL RNS 7SC 8FD JQ2 L7M L~C L~D |
| ID | FETCH-LOGICAL-i208t-4079e0060f919e8550b5a2ab09ad347da75f28da0e56a0ce5291c5af9798206b3 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 1 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000387128200240&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| IngestDate | Fri Jul 11 08:26:04 EDT 2025 Wed Aug 27 02:06:56 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-i208t-4079e0060f919e8550b5a2ab09ad347da75f28da0e56a0ce5291c5af9798206b3 |
| Notes | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Conference-1 ObjectType-Feature-3 content type line 23 SourceType-Conference Papers & Proceedings-2 |
| PQID | 1835664347 |
| PQPubID | 23500 |
| PageCount | 6 |
| ParticipantIDs | proquest_miscellaneous_1835664347 ieee_primary_7546282 |
| PublicationCentury | 2000 |
| PublicationDate | 20151201 |
| PublicationDateYYYYMMDD | 2015-12-01 |
| PublicationDate_xml | – month: 12 year: 2015 text: 20151201 day: 01 |
| PublicationDecade | 2010 |
| PublicationTitle | Proceedings (International Confernce on Computational Intelligence and Communication Networks) |
| PublicationTitleAbbrev | CICN |
| PublicationYear | 2015 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| SSID | ssj0001615872 |
| Score | 1.5846453 |
| Snippet | This paper is focused on the synthesis and simulation of RC4 algorithm, which can be implemented on FPGA. A variable length key from 1 to 16 bytes is used by... |
| SourceID | proquest ieee |
| SourceType | Aggregation Database Publisher |
| StartPage | 1177 |
| SubjectTerms | Algorithms Arrays Ciphers Ciphertext Computer simulation Encryption Field programmable gate arrays Generators Hardware key scheduling algorithm plaintext pseudorandom number generation Software Software algorithms Synthesis Texts |
| Title | Synthesis and Simulation of FPGA Based Hardware Design of RC4 Stream Cipher |
| URI | https://ieeexplore.ieee.org/document/7546282 https://www.proquest.com/docview/1835664347 |
| WOSCitedRecordID | wos000387128200240&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LSwMxEB5q8eCpaiu-ieDRbbfZzWZz1NWqCKVYhd6WbB6wh-5KH4r_3sx22x704i0QAmGSzCMz830A19Z5yTSSzFOMcy8MlPVk5mcez9yNcaFYFDNdkU3w4TCeTMSoATebXhhjTFV8Zro4rHL5ulRL_CrrcYadlE7h7nAerXq1tv8pzjTHnG5hNHvJczLE2i3Wpci1XpGn_NK4lRkZtP63gX3obPvxyGhjaQ6gYYpDaK0JGUj9PtvwMv4unEM3z-dEFpqM82lNzkVKSwajx1ty54yWJpiu_5IzQ-6r-g2cfU1CghlqOSVJjlADHXgfPLwlT17NluDl1I8XLhDkwiC8ihV9YRCnLGOSOsELqYOQa8mZpbGWvmGR9JVhVPQVk1ZwgRjuWXAEzaIszDGQ2ASBdXFSP0AgByGzzFop4iBiRlGt5Am0UTbpxwoQI63FcgJXa-Gm7pJi5kEWplzOU6c3nNsYum2c_r30DPbwpFZ1IufQXMyW5gJ21ecin88uq5P-Ab1PqKo |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3NT8IwFG8ImugJFYz4WROPjo9uXdejThECLkQw4bZ0a5vswGYYaPzv7RsDDnrx1qRp0ry276Pvvd8PoTttvGTiCmrFlDHLsWNtiagTWSwyN8aEYq5HZUE2wYLAm834uILut70wSqmi-Ey1YFjk8mUWr-CrrM0odFIahbsHzFllt9buR8UYZ4-RHZBm2x_4AVRv0RYBtvWCPuWXzi0MSa_2vy0cocauIw-Pt7bmGFVUeoJqG0oGXL7QOhpOvlPj0uVJjkUq8SSZl_RcONO4N355wI_GbEkMCfsvsVD4qajggNk338GQoxZz7CcANtBA773nqd-3Sr4EKyEdb2lCQcYVAKxo3uUKkMoiKogRPRfSdpgUjGriSdFR1BWdWFHCuzEVmjMOKO6RfYqqaZaqM4Q9ZdvaREpdG6AcuIgirQX3bJeqmMhYNFEdZBN-rCExwlIsTXS7EW5orinkHkSqslUeGs1hHEfHbOP876U36KA_fR2Fo0EwvECHcGrrqpFLVF0uVuoK7cefyyRfXBen_gO1V6vz |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=proceeding&rft.title=Proceedings+%28International+Confernce+on+Computational+Intelligence+and+Communication+Networks%29&rft.atitle=Synthesis+and+Simulation+of+FPGA+Based+Hardware+Design+of+RC4+Stream+Cipher&rft.au=Sonawane%2C+Pradeep+J.&rft.au=Bhadade%2C+Umesh+S.&rft.date=2015-12-01&rft.pub=IEEE&rft.eissn=2472-7555&rft.spage=1177&rft.epage=1182&rft_id=info:doi/10.1109%2FCICN.2015.228&rft.externalDocID=7546282 |