Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating

We address a new problem of transforming the long toggling/untoggling sequences of flip-flops' cycle-accurate activities into short embedding vectors, so that the flip-flop grouping for clock gating is practically feasible in terms of the memory usage and run time for checking activity similari...

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Vydané v:	IEEE International Symposium on Circuits and Systems proceedings s. 1 - 5
Hlavní autori:	Park, Sora, Kim, Taewhan
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 21.05.2023
Predmet:	Circuits and systems clock gating flip-flop grouping Integrated circuit modeling Long short term memory low-power design Machine learning Neural networks Noise reduction Predictive models
ISSN:	2158-1525
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