Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating

We address a new problem of transforming the long toggling/untoggling sequences of flip-flops' cycle-accurate activities into short embedding vectors, so that the flip-flop grouping for clock gating is practically feasible in terms of the memory usage and run time for checking activity similari...

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Vydáno v:IEEE International Symposium on Circuits and Systems proceedings s. 1 - 5
Hlavní autoři: Park, Sora, Kim, Taewhan
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 21.05.2023
Témata:
Circuits and systems
clock gating
flip-flop grouping
Integrated circuit modeling
Long short term memory
low-power design
Machine learning
Neural networks
Noise reduction
Predictive models
ISSN:2158-1525
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Popis
Shrnutí:We address a new problem of transforming the long toggling/untoggling sequences of flip-flops' cycle-accurate activities into short embedding vectors, so that the flip-flop grouping for clock gating is practically feasible in terms of the memory usage and run time for checking activity similarity among flip-flops. To this end, we propose a machine learning based generation of embedding vectors which are accurate enough to predict the original flip-flop toggling sequences. Precisely, we develop a neural network model of LSTM (long short-term memory) based AE (autoencoder) model combined with SDAE (stacked denoising autoencoder) to take into account the time-series (i.e., clock cycle) similarity feature among the toggling sequences, which is essential to determine which flip-flops should be grouped together for clock gating. By integrating (1) our LSTM based embedding vector generation model, we propose two additional ML models for clock gating: (2) joint state probability predictor (JSP) model for generating 0-state probability of two embedding vectors, and (3) joint feature predictor (JFP) model for generating a new embedding vector that combines two embedding vectors.
ISSN:2158-1525
DOI:10.1109/ISCAS46773.2023.10181800