Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation

The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains. This paper proposes a benchmarking framework tailored specifically for evaluating LLM performance in the context of Verilog code generation for hardware design and verification. We p...

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Vydané v:	Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design s. 1 - 8
Hlavní autori:	Liu, Mingjie, Pinckney, Nathaniel, Khailany, Brucek, Ren, Haoxing
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 28.10.2023
Predmet:	Benchmark testing Codes Combinational circuits Design automation Distance measurement Hardware Hardware design languages
ISSN:	1558-2434
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