Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications

Applications with low data reuse and frequent irregular memory accesses, such as graph or sparse linear algebra workloads, fail to scale well due to memory bottlenecks and poor core utilization. While prior work with prefetching, decoupling, or pipelining can mitigate memory latency and improve core...

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Vydané v:	Proceedings - International Symposium on High-Performance Computer Architecture s. 718 - 730
Hlavní autori:	Orenes-Vera, Marcelo, Tureci, Esin, Wentzlaff, David, Martonosi, Margaret
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 01.02.2023
Predmet:	architecture bandwidth data-local Distributed graph near-memory network NoC parallel scalable sparse
ISSN:	2378-203X
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