SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs

Various verification methods have been proposed for bug detection in central processing unit (CPU) designs, yet their effectiveness remains insufficient. We have observed that such CPU bugs often occur in exceptional handling, such as pipeline stalls and flushes. We found that corner cases in such e...

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Vydáno v:Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design s. 1 - 9
Hlavní autoři: Sugiyama, Yuichi, Matsuo, Reoma, Shioya, Ryota
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 28.10.2023
Témata:
Annotations
Computer bugs
CPU verification
Design automation
Design methodology
Directed fuzzing
Fuzzing
Hardware
Pipelines
RISC-V
ISSN:1558-2434
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Shrnutí:Various verification methods have been proposed for bug detection in central processing unit (CPU) designs, yet their effectiveness remains insufficient. We have observed that such CPU bugs often occur in exceptional handling, such as pipeline stalls and flushes. We found that corner cases in such exceptional handling can be effectively verified through situations we term a 'surge'. A surge refers to a situation where events leading to exceptional handling occur frequently over a short period of time. For instance, a surge caused by frequent queue insertions can eventually fill the capacity, triggering exceptional handling such as a pipeline stall. We propose a novel fuzzing method for CPU designs, named SurgeFuzz, that intentionally generates surges. SurgeFuzz mutates input instruction sequences based on annotations to increase the occurrence of surges. This results in a higher density of event occurrences, thereby enabling efficient verification of corner cases in exceptional handling. We evaluated SurgeFuzz on a large processor design and found several unknown hardware bugs that are difficult to find with existing methods.
ISSN:1558-2434
DOI:10.1109/ICCAD57390.2023.10323819