AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning
Recent years have seen a rapid increase in research activity in the field of DRAM-based Processing-In-Memory (PIM) accelerators, where the analog computing capability of DRAM is employed by minimally changing the inherent structure of DRAM peripherals to accelerate various data-centric applications....
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| Vydáno v: | Proceedings / IEEE International Symposium on Quality Electronic Design s. 1 - 8 |
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05.04.2023
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| ISSN: | 1948-3295 |
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| Abstract | Recent years have seen a rapid increase in research activity in the field of DRAM-based Processing-In-Memory (PIM) accelerators, where the analog computing capability of DRAM is employed by minimally changing the inherent structure of DRAM peripherals to accelerate various data-centric applications. Several DRAM-based PIM accelerators for Convolutional Neural Networks (CNNs) have also been reported. Among these, the accelerators leveraging in-DRAM stochastic arithmetic have shown manifold improvements in processing latency and throughput, due to the ability of stochastic arithmetic to convert multiplications into simple bit-wise logical AND operations. However, the use of in-DRAM stochastic arithmetic for CNN acceleration requires frequent stochastic to binary number conversions. For that, prior works employ full adder-based or serial counter-based in-DRAM circuits. These circuits consume large area and incur long latency. Their in-DRAM implementations also require heavy modifications in DRAM peripherals, which significantly diminishes the benefits of using stochastic arithmetic in these accelerators. To address these shortcomings, this paper presents a new substrate for in-DRAM stochastic-to-binary number conversion called AGNI. AGNI makes minor modifications in DRAM peripherals using pass transistors, capacitors, encoders, and charge pumps, and re-purposes the sense amplifiers as voltage comparators, to enable in-situ binary conversion of input statistic operands of different sizes with iso latency. Our evaluations, based on detailed SPICE simulations (https://github.com/uky-UCAT/AGNI_SPICE.git), show that AGNI can achieve savings of at least 8× in area, at least 28× energy-delay product (EDP), and at least 21 in area × latency, compared to two in-DRAM stochastic-to-binary conversion circuits from prior works. These circuit-level benefits are demonstrated to propagate at the system-level to achieve at least 3.9× gain in performance across four deep CNN models. |
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| AbstractList | Recent years have seen a rapid increase in research activity in the field of DRAM-based Processing-In-Memory (PIM) accelerators, where the analog computing capability of DRAM is employed by minimally changing the inherent structure of DRAM peripherals to accelerate various data-centric applications. Several DRAM-based PIM accelerators for Convolutional Neural Networks (CNNs) have also been reported. Among these, the accelerators leveraging in-DRAM stochastic arithmetic have shown manifold improvements in processing latency and throughput, due to the ability of stochastic arithmetic to convert multiplications into simple bit-wise logical AND operations. However, the use of in-DRAM stochastic arithmetic for CNN acceleration requires frequent stochastic to binary number conversions. For that, prior works employ full adder-based or serial counter-based in-DRAM circuits. These circuits consume large area and incur long latency. Their in-DRAM implementations also require heavy modifications in DRAM peripherals, which significantly diminishes the benefits of using stochastic arithmetic in these accelerators. To address these shortcomings, this paper presents a new substrate for in-DRAM stochastic-to-binary number conversion called AGNI. AGNI makes minor modifications in DRAM peripherals using pass transistors, capacitors, encoders, and charge pumps, and re-purposes the sense amplifiers as voltage comparators, to enable in-situ binary conversion of input statistic operands of different sizes with iso latency. Our evaluations, based on detailed SPICE simulations (https://github.com/uky-UCAT/AGNI_SPICE.git), show that AGNI can achieve savings of at least 8× in area, at least 28× energy-delay product (EDP), and at least 21 in area × latency, compared to two in-DRAM stochastic-to-binary conversion circuits from prior works. These circuit-level benefits are demonstrated to propagate at the system-level to achieve at least 3.9× gain in performance across four deep CNN models. |
| Author | Salehi, Sayed Ahmad Vatsavai, Sairam Sri Thakkar, Ishan Shivanandamurthy, Supreeth Mysore |
| Author_xml | – sequence: 1 givenname: Supreeth Mysore surname: Shivanandamurthy fullname: Shivanandamurthy, Supreeth Mysore organization: University of Kentucky,Department of Electrical and Computer Engineering,Lexington,KY,USA,40506 – sequence: 2 givenname: Sairam Sri surname: Vatsavai fullname: Vatsavai, Sairam Sri organization: University of Kentucky,Department of Electrical and Computer Engineering,Lexington,KY,USA,40506 – sequence: 3 givenname: Ishan surname: Thakkar fullname: Thakkar, Ishan organization: University of Kentucky,Department of Electrical and Computer Engineering,Lexington,KY,USA,40506 – sequence: 4 givenname: Sayed Ahmad surname: Salehi fullname: Salehi, Sayed Ahmad organization: University of Kentucky,Department of Electrical and Computer Engineering,Lexington,KY,USA,40506 |
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| Snippet | Recent years have seen a rapid increase in research activity in the field of DRAM-based Processing-In-Memory (PIM) accelerators, where the analog computing... |
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| SubjectTerms | Convolutional neural networks processing-in-memory Random access memory SPICE Stochastic processes stochastic to binary conversion Throughput Transistors Voltage |
| Title | AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning |
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