Design of a teaching computer with floating point unit for Computer Architecture

The computer used in Computer Architecture practices of Computer Engineering at the University of Cordoba does not allow the development of floating-point instructions. As several arithmetic algorithms developed in floating-point are taught in the subject, the design of a new computer that includes...

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Vydané v:2020 XIV Technologies Applied to Electronics Teaching Conference (TAEE) s. 1 - 8
Hlavní autori: Gersnoviez, Andres, Brox, Maria, Castillo-Marquez, Carlos, Montijano-Vizcaino, Miguel A., Ortiz-Lopez, Manuel A., Quiles-Latorre, Francisco J.
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 01.07.2020
Predmet:
Computer architecture
Computer Architecture practices
Education
Floating-point arithmetic
Ground penetrating radar
OrCAD software
Random access memory
Registers
Writing
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Shrnutí:The computer used in Computer Architecture practices of Computer Engineering at the University of Cordoba does not allow the development of floating-point instructions. As several arithmetic algorithms developed in floating-point are taught in the subject, the design of a new computer that includes an arithmetic-logical unit (ALU) capable of implementing them is presented in this paper. The work describes the structure of the new computer, the floating-point number format chosen and the correct implementation of different floating-point algorithms. The new computer allows that students understand in a more optimal way the theoretical concepts taught about floating-point arithmetic.
DOI:10.1109/TAEE46915.2020.9163737