Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design

The emergence of High-Level Synthesis (HLS) tools shifted the paradigm of hardware design by making the process of mapping high-level programming languages to hardware design such as C to VHDL/Verilog feasible. HLS tools offer a plethora of techniques to optimize designs for both area and performanc...

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Veröffentlicht in:	International Conference on Field-programmable Logic and Applications S. 397 - 403
Hauptverfasser:	Mohammadi Makrani, Hosein, Farahmand, Farnoud, Sayadi, Hossein, Bondi, Sara, Pudukotai Dinakarrao, Sai Manoj, Homayoun, Houman, Rafatirad, Setareh
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 01.09.2019
Schlagworte:	Clocks ensemble learning Field programmable gate arrays Hardware HLS Optimization Throughput Timing timing estimation
ISSN:	1946-1488
Online-Zugang:	Volltext
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