Partial Order Pruning: For Best Speed/Accuracy Trade-Off in Neural Architecture Search
Achieving good speed and accuracy trade-off on a target platform is very important in deploying deep neural networks in real world scenarios. However, most existing automatic architecture search approaches only concentrate on high performance. In this work, we propose an algorithm that can offer bet...
Gespeichert in:
| Veröffentlicht in: | Proceedings (IEEE Computer Society Conference on Computer Vision and Pattern Recognition. Online) S. 9137 - 9145 |
|---|---|
| Hauptverfasser: | , , , |
| Format: | Tagungsbericht |
| Sprache: | Englisch |
| Veröffentlicht: |
IEEE
01.06.2019
|
| Schlagworte: | |
| ISSN: | 1063-6919 |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Abstract | Achieving good speed and accuracy trade-off on a target platform is very important in deploying deep neural networks in real world scenarios. However, most existing automatic architecture search approaches only concentrate on high performance. In this work, we propose an algorithm that can offer better speed/accuracy trade-off of searched networks, which is termed "Partial Order Pruning''. It prunes the architecture search space with a partial order assumption to automatically search for the architectures with the best speed and accuracy trade-off. Our algorithm explicitly takes profile information about the inference speed on the target platform into consideration. With the proposed algorithm, we present several Dongfeng (DF) networks that provide high accuracy and fast inference speed on various application GPU platforms. By further searching decoder architectures, our DF-Seg real-time segmentation networks yield state-of-the-art speed/accuracy trade-off on both the {target embedded device} and the high-end GPU. |
|---|---|
| AbstractList | Achieving good speed and accuracy trade-off on a target platform is very important in deploying deep neural networks in real world scenarios. However, most existing automatic architecture search approaches only concentrate on high performance. In this work, we propose an algorithm that can offer better speed/accuracy trade-off of searched networks, which is termed "Partial Order Pruning''. It prunes the architecture search space with a partial order assumption to automatically search for the architectures with the best speed and accuracy trade-off. Our algorithm explicitly takes profile information about the inference speed on the target platform into consideration. With the proposed algorithm, we present several Dongfeng (DF) networks that provide high accuracy and fast inference speed on various application GPU platforms. By further searching decoder architectures, our DF-Seg real-time segmentation networks yield state-of-the-art speed/accuracy trade-off on both the {target embedded device} and the high-end GPU. |
| Author | Feng, Jiashi Pan, Zheng Zhou, Yiming Li, Xin |
| Author_xml | – sequence: 1 givenname: Xin surname: Li fullname: Li, Xin organization: UISEE Technology – sequence: 2 givenname: Yiming surname: Zhou fullname: Zhou, Yiming organization: Univ. of Electrical Science and Technology of China – sequence: 3 givenname: Zheng surname: Pan fullname: Pan, Zheng organization: UISEE Company – sequence: 4 givenname: Jiashi surname: Feng fullname: Feng, Jiashi organization: NUS |
| BookMark | eNotjE1PAjEUAKvRRETOHrz0Dyy812bbfd6QiJoQIYJcST_eag0upLsc-PeQ6Gkyc5hbcdXsGhbiHmGICDSarBcfQwVIQwDS5kIMyFZoVYVaka4uRQ_B6MIQ0o0YtO0PAGiFaKjqifXC5S65rZznyFku8qFJzdejnO6yfOK2k8s9cxyNQzhkF45ylV3kYl7XMjXync9xK8c5fKeOQ3fILJfsznonrmu3bXnwz774nD6vJq_FbP7yNhnPiqRAd0WwhhUqBAtUUvAclY4K2PtKeSyJyBlflrUHH6hE62Lto7LoAKwxodR98fD3Tcy82ef06_JxU1GpKyJ9Ag4sUmQ |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IH CBEJK RIE RIO |
| DOI | 10.1109/CVPR.2019.00936 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP) 1998-present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Applied Sciences |
| EISBN | 9781728132938 1728132932 |
| EISSN | 1063-6919 |
| EndPage | 9145 |
| ExternalDocumentID | 8953899 |
| Genre | orig-research |
| GroupedDBID | 6IE 6IH 6IL 6IN AAWTH ABLEC ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO IEGSK IJVOP OCL RIE RIL RIO |
| ID | FETCH-LOGICAL-i203t-c76e2121070959cbed23d20ebb82b15999a6b55fb0bc9517adfbd271a00766c53 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 127 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000542649302077&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| IngestDate | Wed Sep 10 07:40:42 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-i203t-c76e2121070959cbed23d20ebb82b15999a6b55fb0bc9517adfbd271a00766c53 |
| PageCount | 9 |
| ParticipantIDs | ieee_primary_8953899 |
| PublicationCentury | 2000 |
| PublicationDate | 2019-June |
| PublicationDateYYYYMMDD | 2019-06-01 |
| PublicationDate_xml | – month: 06 year: 2019 text: 2019-June |
| PublicationDecade | 2010 |
| PublicationTitle | Proceedings (IEEE Computer Society Conference on Computer Vision and Pattern Recognition. Online) |
| PublicationTitleAbbrev | CVPR |
| PublicationYear | 2019 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| SSID | ssj0003211698 |
| Score | 2.5461874 |
| Snippet | Achieving good speed and accuracy trade-off on a target platform is very important in deploying deep neural networks in real world scenarios. However, most... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 9137 |
| SubjectTerms | Accuracy Computer architecture Computer vision Decoding Deep Learning Graphics processing units Grouping and Shape Inference algorithms Network architecture Neural architecture search Pattern recognition Real-time systems Segmentation |
| Title | Partial Order Pruning: For Best Speed/Accuracy Trade-Off in Neural Architecture Search |
| URI | https://ieeexplore.ieee.org/document/8953899 |
| WOSCitedRecordID | wos000542649302077&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LSwMxEA5t8eCpaiu-ycGjsfvKJvFWi8WDtIuP0lvJYwIF2ZZtV_Dfm-wutQcv3kIgCcyQzOSbmW8QupU2BWp1QFhiDEmM1kTGqSLOWUi0NFwKW2n6hU0mfD4XWQvd7WphAKBKPoN7P6xi-WalSw-VDbigng6ujdqMsbpWa4enxO4nkwresPeEgRiMZtmrz93yhJTCUzDvtU-prMe4-79zj1D_twwPZzsDc4xakJ-gbuM34uZWbnpolnn9y0889TyabknpwY4HPF4V-NG9-vht7bYYDLUuC6m_sbNPBsjUWrzMsWfncEuHewEFXOcg99HH-Ol99EyafglkGQXxlmiWQuQJwZgH97QCE8UmCkApHinntgghU0WpVYHSzrFi0lhlIhZKH45LNY1PUSdf5XCGMIeQSkq58s2pUxpyAzEHa5lMogjC5Bz1vJgW65oSY9FI6OLv6Ut06PVQZ1hdoc62KOEaHeiv7XJT3FR6_AEa1Z-G |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3NT8IwFG8QTfSECsZve_BoZevWrfWGRIIRYVEk3Eg_ExIzyGAm_ve224IcvHhrmrw2ea_te30fvwfALTeRJkZ6KA6VQqGSEvEgEsgaC6HkinJmCkkP4uGQTqcsqYG7TS2M1rpIPtP3bljE8tVC5s5V1qaMODi4HbBLwhD7ZbXWxqMS2L9MxGiF3-N7rN2dJG8ue8tBUjIHwrzVQKXQH73G_3Y-BK3fQjyYbFTMEajp9Bg0KssRVvdy1QSTxJ0A_glHDknTkuTO3fEAe4sMPtp3H74v7RLtjpR5xuU3tBpKaTQyBs5T6PA5LGlnK6QAyyzkFvjoPY27fVR1TEBz7AVrJONIYwcJFjv3nhRa4UBhTwtBsbCGC2M8EoQY4QlpTauYKyMUjn3uAnKRJMEJqKeLVJ8CSLVPOCFUuPbUEfGp0gHVxsQ8xFj74RloOjbNliUoxqzi0Pnf0zdgvz9-HcwGz8OXC3DgZFLmW12C-jrL9RXYk1_r-Sq7LmT6A5dFos0 |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Proceedings+%28IEEE+Computer+Society+Conference+on+Computer+Vision+and+Pattern+Recognition.+Online%29&rft.atitle=Partial+Order+Pruning%3A+For+Best+Speed%2FAccuracy+Trade-Off+in+Neural+Architecture+Search&rft.au=Li%2C+Xin&rft.au=Zhou%2C+Yiming&rft.au=Pan%2C+Zheng&rft.au=Feng%2C+Jiashi&rft.date=2019-06-01&rft.pub=IEEE&rft.eissn=1063-6919&rft.spage=9137&rft.epage=9145&rft_id=info:doi/10.1109%2FCVPR.2019.00936&rft.externalDocID=8953899 |