HiPReP: High-Performance Reconfigurable Processor - Architecture and Compiler

The computational parallelism and energy efficiency inherent in reconfigurable hardware architectures like finegrained Field-Programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Arrays (CGRAs) have been a subject of research mostly for Multimedia applications for many years [1]. The sa...

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Veröffentlicht in:International Conference on Field-programmable Logic and Applications S. 380 - 381
Hauptverfasser: Kasgen, Philipp, Messelka, Mohamed, Weinhardt, Markus
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.08.2021
Schlagworte:
C compiler
CGRA
Computational efficiency
Computer architecture
Energy efficiency
Field programmable gate arrays
FPU
Hardware
HPC
Multicore processing
Parallel processing
Reconfigurable Computing
ISSN:1946-1488
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Zusammenfassung:The computational parallelism and energy efficiency inherent in reconfigurable hardware architectures like finegrained Field-Programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Arrays (CGRAs) have been a subject of research mostly for Multimedia applications for many years [1]. The said strengths of reconfigurable systems are also beneficial for other application domains, e.g. High-Performance Computing (HPC), since single-core and multicore systems may soon hit scaling limits.
ISSN:1946-1488
DOI:10.1109/FPL53798.2021.00074