High performance code generation for VLIW digital signal processors

VLIW (Very Long Instruction Word) architecture has been widely adopted in latest digital signal processor designs to meet the ever increasing need of computing power in, e.g. multimedia applications. In this paper, we present an efficient and retargetable code generation tool for VLIW based DSPs. To...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528) S. 683 - 692
Hauptverfasser: Yin-Tsung Hwang, Ying-Chou Chuang
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 2000
Schlagworte:
Computer aided instruction
Computer architecture
Digital signal processing
Digital signal processors
Multimedia computing
Pipeline processing
Process design
Signal design
Signal generators
VLIW
ISBN:0780364880, 9780780364882
ISSN:1520-6130
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Abstract VLIW (Very Long Instruction Word) architecture has been widely adopted in latest digital signal processor designs to meet the ever increasing need of computing power in, e.g. multimedia applications. In this paper, we present an efficient and retargetable code generation tool for VLIW based DSPs. To make the code generation tool retargetable, we first developed a versatile coding constraint model to faithfully characterize the target machine's limitations on hardware resource, pipeline execution and other specific instruction usage. Second, since loop executions account for most of the time consumption, the software pipelining technique was employed to overlap the execution of successive iterations. To generate efficient code for real time applications, a simulated evolution (SE) based code generation module was introduced to derive the steady state loop scheduling. Effective heuristics subject to various coding constraints were developed. In addition, to alleviate the scheduling overhead in checking coding/resource constraints repetitively, bit-parallel verification schemes was devised as well. Several test benches on TI TMS320C62/67X DSP have been conducted to verify the effectiveness of our tool and preliminary results show that it can achieve near hand optimized quality code.
AbstractList VLIW (Very Long Instruction Word) architecture has been widely adopted in latest digital signal processor designs to meet the ever increasing need of computing power in, e.g. multimedia applications. In this paper, we present an efficient and retargetable code generation tool for VLIW based DSPs. To make the code generation tool retargetable, we first developed a versatile coding constraint model to faithfully characterize the target machine's limitations on hardware resource, pipeline execution and other specific instruction usage. Second, since loop executions account for most of the time consumption, the software pipelining technique was employed to overlap the execution of successive iterations. To generate efficient code for real time applications, a simulated evolution (SE) based code generation module was introduced to derive the steady state loop scheduling. Effective heuristics subject to various coding constraints were developed. In addition, to alleviate the scheduling overhead in checking coding/resource constraints repetitively, bit-parallel verification schemes was devised as well. Several test benches on TI TMS320C62/67X DSP have been conducted to verify the effectiveness of our tool and preliminary results show that it can achieve near hand optimized quality code.
Author Yin-Tsung Hwang
Ying-Chou Chuang
Author_xml – sequence: 1
  surname: Yin-Tsung Hwang
  fullname: Yin-Tsung Hwang
  organization: Inst. of Electron. & Inf. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
– sequence: 2
  surname: Ying-Chou Chuang
  fullname: Ying-Chou Chuang
BookMark eNotj09LwzAYhwNOcJu7i6d8gdY3SZM0RynqCgWF-ec42vRNjWxNSXrx21uYp-fw_HjgtyGrMYxIyB2DnDEwD4f67ZBzAMjLUmmlrsgGdAlCFWUJK7JmkkOmmIAbskvpZxkyzqQ2Zk2qvR--6YTRhXhuR4vUhh7pgCPGdvZhpIugn039RXs_-Lk90eSHccEUg8WUQky35Nq1p4S7f27Jx_PTe7XPmteXunpsMs9BzJnpOBZOG5RaGLCl6TpECZ3uLXeWLdIyrfpCtVxIhxJdZznrDefGomZabMn9pesR8ThFf27j7_FyWfwBYPBMkA
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/SIPS.2000.886766
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EndPage 692
ExternalDocumentID 886766
GroupedDBID 6IE
6IL
ABLEC
AFFNX
ALMA_UNASSIGNED_HOLDINGS
CBEJK
IEGSK
RIE
RIL
ID FETCH-LOGICAL-i203t-9b2e4f79e57390c89bbee50b7dc2fc12e4c176d46a235fe5efbc21d9229ce7173
IEDL.DBID RIE
ISBN 0780364880
9780780364882
ISICitedReferencesCount 1
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000165893400068&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
ISSN 1520-6130
IngestDate Tue Aug 26 18:17:20 EDT 2025
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i203t-9b2e4f79e57390c89bbee50b7dc2fc12e4c176d46a235fe5efbc21d9229ce7173
PageCount 10
ParticipantIDs ieee_primary_886766
PublicationCentury 2000
PublicationDate 20000000
PublicationDateYYYYMMDD 2000-01-01
PublicationDate_xml – year: 2000
  text: 20000000
PublicationDecade 2000
PublicationTitle 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528)
PublicationTitleAbbrev SIPS
PublicationYear 2000
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0001215799
ssj0020401
Score 1.3059651
Snippet VLIW (Very Long Instruction Word) architecture has been widely adopted in latest digital signal processor designs to meet the ever increasing need of computing...
SourceID ieee
SourceType Publisher
StartPage 683
SubjectTerms Computer aided instruction
Computer architecture
Digital signal processing
Digital signal processors
Multimedia computing
Pipeline processing
Process design
Signal design
Signal generators
VLIW
Title High performance code generation for VLIW digital signal processors
URI https://ieeexplore.ieee.org/document/886766
WOSCitedRecordID wos000165893400068&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV27bsIwFLUK6tAubSlV3_LQNZDY8WtGRUWqEBJ9sKHEvkYsgCD0--tHKFTq0ilOrCiRbdk699xzLkJP1qQFt4ImANwBFMkhUaqwCVc5cEYkYxCLTYjhUE4malT7bActDACE5DPo-Gbg8s1Sb32orCslF5w3UEMIHqVaB-GUjAWCqsZabm1Gq9SAjmgaELv0pJtbsLXxzu6e7OjLVHXHg9E4yFc68WO_iq6EM6d_9q-_PUftvXYPj35OpQt0BIsWOj2wHbxEPZ_cgVd7yQD2wnY8Cw7UfqKw68Afr4NPbOYzX1UE-zQPd1lFWcFyvWmj9_7zW-8lqYspJHOS0ipRJYHcCgVMUJVqqcoSgKWlMJpYnblOnQlucl4QyiwwsKUmmVGEKA2eqr9CzcVyAdcIu32JSpNbTRVz6E6rsqCQlVS4V4lDlDeo5Udjuop-GdM4ELd_Pr1DJ1Hc7oMa96hZrbfwgI71VzXfrB_DHH8DlEegOw
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3LTsJAFJ0omqgbFTG-nYXbQjvTea2NBCISElDZkXZ6h7ABwsPvdx5FMHHjqo9J02bupJNz7z3nIPRkijjjRtAIgFuAIjlESmUm4ioFzohkDILZhOh25XCoeqXOtufCAIBvPoO6O_W1_GKm1y5V1pCSC8730YEzzirJWjsJlYT5ElWJtuzqDGKpHh_R2GN26cpudsmW0juba7IpYMaq0W_3-p7AUg-v-2W74ned5um_vvcM1bbsPdz72ZfO0R5Mq-hkR3jwAj279g4835IGsKO247HXoHahwnYAf3Tan7iYjJ2vCHaNHvYwD8SC2WJZQ-_Nl8FzKyrtFKIJiekqUjmB1AgFTFAVa6nyHIDFuSg0MTqxgzoRvEh5RigzwMDkmiSFIkRpcMX6S1SZzqZwhbD9M1FZpEZTZUMhtcozCklOhX2UWEx5japuNkbzoJgxChNx8-fdR3TUGrx1Rp129_UWHQequ0tx3KHKarGGe3Sov1aT5eLBx_sbJYujhA
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2000+IEEE+Workshop+on+SiGNAL+PROCESSING+SYSTEMS.+SiPS+2000.+Design+and+Implementation+%28Cat.+No.00TH8528%29&rft.atitle=High+performance+code+generation+for+VLIW+digital+signal+processors&rft.au=Yin-Tsung+Hwang&rft.au=Ying-Chou+Chuang&rft.date=2000-01-01&rft.pub=IEEE&rft.isbn=9780780364882&rft.issn=1520-6130&rft.spage=683&rft.epage=692&rft_id=info:doi/10.1109%2FSIPS.2000.886766&rft.externalDocID=886766
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1520-6130&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1520-6130&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1520-6130&client=summon