High Speed Floating Point Multiply Accumulate Unit using Offset Binary Coding

This paper deals with less delay efficient multiplier and accumulator unit for inner product, filtering [3] applications, convolution, image and video processing applications etc., Multiply and Accumulate unit plays and important role in Digital signal processor. On designing this consumes large are...

Full description

Bibliographic Details

Published in:	2020 7th International Conference on Smart Structures and Systems (ICSSS) pp. 1 - 5
Main Authors:	Lahari, P.L., Bharathi, M., Shirur, Yasha Jyothi M
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.07.2020
Subjects:	Adders Conferences Delays Distributed Arithmetic Encoding floating point Floating-point arithmetic Multiply Accumulate Unit Offset binary coding Read only memory
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!