Scalable elliptic curve encryption processor for portable application

This paper presents the design and implementation of an energy efficient, scalable elliptic curve encryption processor over GF(2 m ) for portable application. The proposed processor contains three hierarchical controllers and one reconfigurable datapath to operate various finite field arithmetic. Sc...

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Published in:ASIC, 2003. Proceedings. 5th International Conference on Vol. 2; pp. 1312 - 1316 Vol.2
Main Authors: Chi Huang, Jinmei Lai, Junyan Ren, Qianling Zhang
Format: Conference Proceeding
Language:English
Published: IEEE 2003
ISBN:0780378946, 078037889X, 9780780378940, 9780780378896
ISSN:1523-553X
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Abstract This paper presents the design and implementation of an energy efficient, scalable elliptic curve encryption processor over GF(2 m ) for portable application. The proposed processor contains three hierarchical controllers and one reconfigurable datapath to operate various finite field arithmetic. Scalable register is used to fit different elliptic curves and alterable field degree m (from 149 to 251), so the power is not wasted by the extra registers switching. In order to realize the reconfigurable architecture for portable application, we also adopt Montgomery's affine algorithm, MSB-first bit-serial multiplication and an extended binary Euclidean algorithm to perform an inversion computation efficiently. The processor is implemented using 0.35 μm CMOS process. The core area is 2.75mm 2 with the peak frequency of 100MHz. This processor do one point multiplication in 5.5 ms over GF(2 251 ) and its maximum power consumption is only 13.6mW.
AbstractList This paper presents the design and implementation of an energy efficient, scalable elliptic curve encryption processor over GF(2 m ) for portable application. The proposed processor contains three hierarchical controllers and one reconfigurable datapath to operate various finite field arithmetic. Scalable register is used to fit different elliptic curves and alterable field degree m (from 149 to 251), so the power is not wasted by the extra registers switching. In order to realize the reconfigurable architecture for portable application, we also adopt Montgomery's affine algorithm, MSB-first bit-serial multiplication and an extended binary Euclidean algorithm to perform an inversion computation efficiently. The processor is implemented using 0.35 μm CMOS process. The core area is 2.75mm 2 with the peak frequency of 100MHz. This processor do one point multiplication in 5.5 ms over GF(2 251 ) and its maximum power consumption is only 13.6mW.
Author Chi Huang
Qianling Zhang
Jinmei Lai
Junyan Ren
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