Totally self-checking (TSC) VLSI circuits using Scalable Error Detection Coding (SEDC) technique

Integrated circuits fabricated in deep sub-micron technology are vulnerable to intermittent or transient faults which are the predominant cause of system failures. With continued scaling, operating voltage levels have reduced and resultant decrease in noise margins, the possibility of transient faul...

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Veröffentlicht in:	2013 5th Asia Symposium on Quality Electronic Design (ASQED) S. 72 - 79
Hauptverfasser:	Somasundaram, Natarajan, Mehdipour, Farhad, Jeong-A Lee, Ramadass, N., Rao, Y. V. Ramana
Format:	Tagungsbericht
Sprache:	Englisch Japanisch
Veröffentlicht:	IEEE 01.08.2013
Schlagworte:	Circuit faults Computer architecture Dependable Architecture Encoding Error detection coding Fault tolerance Hardware Logic gates Redundancy Totally Self-Checking circuits Transient analysis Unidirectional errors
Online-Zugang:	Volltext
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