A systolic array architecture for implementing a fast parallel decoding algorithm of one-point AG codes

Previously we proposed a fast parallel decoding algorithm for general one-point algebraic geometric (AG) codes with a systolic array architecture. But, designing the detailed structure of the systolic array and scheduling the relevant procedures remained to be given explicitly, because the proper di...

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Bibliographic Details

Published in:	1997 IEEE International Symposium on Information Theory p. 378
Main Authors:	Sakata, S., Kurihara, M.
Format:	Conference Proceeding
Language:	English Japanese
Published:	IEEE 22.11.2002
Subjects:	Computer architecture Computer science Decoding Design methodology Mathematics Polynomials Processor scheduling Proposals Scheduling algorithm Systolic arrays
ISBN:	9780780339569, 0780339568
Online Access:	Get full text
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