Sakata, S., & Kurihara, M. (2002, November 22). A systolic array architecture for implementing a fast parallel decoding algorithm of one-point AG codes. 1997 IEEE International Symposium on Information Theory, 378. https://doi.org/10.1109/ISIT.1997.613315
Chicago-Zitierstil (17. Ausg.)Sakata, S., und M. Kurihara. "A Systolic Array Architecture for Implementing a Fast Parallel Decoding Algorithm of One-point AG Codes." 1997 IEEE International Symposium on Information Theory 22 Nov. 2002: 378. https://doi.org/10.1109/ISIT.1997.613315.
MLA-Zitierstil (9. Ausg.)Sakata, S., und M. Kurihara. "A Systolic Array Architecture for Implementing a Fast Parallel Decoding Algorithm of One-point AG Codes." 1997 IEEE International Symposium on Information Theory, 22 Nov. 2002, p. 378, https://doi.org/10.1109/ISIT.1997.613315.