High-Throughput SAT Sampling
In this work, we present a novel technique for GPU-accelerated Boolean satisfiability (SAT) sampling. Unlike conventional sampling algorithms that directly operate on conjunctive normal form (CNF), our method transforms the logical constraints of SAT problems by factoring their CNF representations i...
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| Published in: | Proceedings - Design, Automation, and Test in Europe Conference and Exhibition pp. 1 - 7 |
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| Format: | Conference Proceeding |
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31.03.2025
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| ISSN: | 1558-1101 |
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| Abstract | In this work, we present a novel technique for GPU-accelerated Boolean satisfiability (SAT) sampling. Unlike conventional sampling algorithms that directly operate on conjunctive normal form (CNF), our method transforms the logical constraints of SAT problems by factoring their CNF representations into simplified multilevel, multi-output Boolean functions. It then leverages gradient-based optimization to guide the search for a diverse set of valid solutions. Our method operates directly on the circuit structure of refactored SAT instances, reinterpreting the SAT problem as a supervised multi-output regression task. This differentiable technique enables independent bit-wise operations on each tensor element, allowing parallel execution of learning processes. As a result, we achieve GPU-accelerated sampling with significant runtime improvements ranging from 33.6x to 523.6x over state-of-the-art heuristic samplers. We demonstrate the superior performance of our sampling method through an extensive evaluation on 60 instances from a public domain benchmark suite utilized in previous studies. |
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| AbstractList | In this work, we present a novel technique for GPU-accelerated Boolean satisfiability (SAT) sampling. Unlike conventional sampling algorithms that directly operate on conjunctive normal form (CNF), our method transforms the logical constraints of SAT problems by factoring their CNF representations into simplified multilevel, multi-output Boolean functions. It then leverages gradient-based optimization to guide the search for a diverse set of valid solutions. Our method operates directly on the circuit structure of refactored SAT instances, reinterpreting the SAT problem as a supervised multi-output regression task. This differentiable technique enables independent bit-wise operations on each tensor element, allowing parallel execution of learning processes. As a result, we achieve GPU-accelerated sampling with significant runtime improvements ranging from 33.6x to 523.6x over state-of-the-art heuristic samplers. We demonstrate the superior performance of our sampling method through an extensive evaluation on 60 instances from a public domain benchmark suite utilized in previous studies. |
| Author | Wawrzynek, John He, Kevin Ardakani, Arash Kang, Minwoo Huang, Qijing |
| Author_xml | – sequence: 1 givenname: Arash surname: Ardakani fullname: Ardakani, Arash email: arash.ardakani@berkeley.edu organization: University of California,Berkeley – sequence: 2 givenname: Minwoo surname: Kang fullname: Kang, Minwoo email: minwoo_kang@berkeley.edu organization: University of California,Berkeley – sequence: 3 givenname: Kevin surname: He fullname: He, Kevin email: kevinjhe@berkeley.edu organization: University of California,Berkeley – sequence: 4 givenname: Qijing surname: Huang fullname: Huang, Qijing email: jennyhuang@nvidia.com organization: NVIDIA – sequence: 5 givenname: John surname: Wawrzynek fullname: Wawrzynek, John email: johnw@berkeley.edu organization: University of California,Berkeley |
| BookMark | eNo1j71OwzAYAA0qEk3LG3TICzj4-_wTe4xKaZEqMTTMle3YiVGbRkk78PYgAdNJN5x0GZn1lz4QkgMrkBswzy9VvVFCoS6QoSyAGcNR6DuScaNRlQJYeU_mIKWmAAweSTZNn4wxydHMyWqX2o7W3Xi5td1wu-aHqs4P9jycUt8uyUO0pyk8_XFBPl439XpH9-_bt3W1pwlKfaXeohVGCsdt451TDpy0SkeIsok_VjsujWWCe2xsaaMulUHwLDp0zkPgC7L67aYQwnEY09mOX8f_Ff4NPJw_jg |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IL CBEJK RIE RIL |
| DOI | 10.23919/DATE64628.2025.10993248 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP All) 1998-Present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering Computer Science |
| EISBN | 3982674107 9783982674100 |
| EISSN | 1558-1101 |
| EndPage | 7 |
| ExternalDocumentID | 10993248 |
| Genre | orig-research |
| GroupedDBID | 6IE 6IF 6IH 6IK 6IL 6IN AAJGR AAWTH ABLEC ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO FEDTE IEGSK IPLJI KZ1 LMP M43 OCL RIE RIL |
| ID | FETCH-LOGICAL-i178t-ca2a4954b3adcbb6b1b5a68f1f5df4b38b359a043c2da7af876921c0fb2bbc1e3 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 0 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=001506972600388&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| IngestDate | Wed Aug 27 01:55:02 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-i178t-ca2a4954b3adcbb6b1b5a68f1f5df4b38b359a043c2da7af876921c0fb2bbc1e3 |
| PageCount | 7 |
| ParticipantIDs | ieee_primary_10993248 |
| PublicationCentury | 2000 |
| PublicationDate | 2025-March-31 |
| PublicationDateYYYYMMDD | 2025-03-31 |
| PublicationDate_xml | – month: 03 year: 2025 text: 2025-March-31 day: 31 |
| PublicationDecade | 2020 |
| PublicationTitle | Proceedings - Design, Automation, and Test in Europe Conference and Exhibition |
| PublicationTitleAbbrev | DATE |
| PublicationYear | 2025 |
| Publisher | EDAA |
| Publisher_xml | – name: EDAA |
| SSID | ssj0005329 |
| Score | 2.2871053 |
| Snippet | In this work, we present a novel technique for GPU-accelerated Boolean satisfiability (SAT) sampling. Unlike conventional sampling algorithms that directly... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 1 |
| SubjectTerms | Benchmark testing Boolean functions Boolean Satisfiability Distance measurement Gradient Descent Logic Multi-level Circuits Optimization Performance gain Runtime Sampling methods Tensors Testing Transforms Verification |
| Title | High-Throughput SAT Sampling |
| URI | https://ieeexplore.ieee.org/document/10993248 |
| WOSCitedRecordID | wos001506972600388&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1JTwIxFH4R4kEvKGJc0MzBa2HamU7bI1GIJ0LCmHAjfV0Ml8Eg-PttZ8Dl4MFb0yVN23R5fd_3PoAHL4wNBZK4IjMkR0yJRKkJtZZKZaT3StdiE2I6lYuFmu3J6jUXxjlXg8_cICZrX75dm138KhtGL054AMgWtIQoGrLWN54jY6qB6rBMUTV8GpXjIjIvgxHI-ODQ9peKSn2JTDr_7P4Met90vGT2ddGcw5GrutA56DEk--3ZhdMfwQUvoB8hHKRsdHhCzWQ-KpO5jgjy6rUHL5Nx-fhM9loIZEWF3BKjmQ62TI6ZtgaxQIpcF9JTz60PuRIzrnSaZ4ZZLbQPh5xi1KQeGaKhLruEdrWu3BUkgoepMsEKdcEiLQyXEmOEnVSj0tLl_Bp6cezLtybcxfIw7Js_8m_hJM5wQ9TrQ3u72bk7ODYf29X75r5epE_XVZI4 |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PT8IwGP2iaKJeUMT4A3UHr4W1Xbf2aBSCEQkJM-FG-tNwGQbBv992A9GDB29Ltyb7urRf3_re9wDuXKaNv8GRTalGiVIx4opLhI3BXGjunJCl2UQ2HPLJRIzWYvVSC2OtLclnth0uy7N8M9er8KusE05x_AaA78IeSzzwqeRaW0YHJaIi6xAqsOg83ufdNGgvPQwkrL3p_ctHpUwjvfo_X-AYmltBXjT6TjUnsGOLBtQ3jgzReoI24OhHecFTaAUSB8orJx7_ZDS-z6OxDBzy4q0Jr71u_tBHazcENMMZXyItifRoJlFUGq1UqrBiMuUOO2acb-WKMiHjhGpiZCadX-YEwTp2iiilsaVnUCvmhT2HKGN-qLTHodZj0lQzzlWosRNLJSS3CbuAZoh9-l4VvJhuwr78o_0WDvr5y2A6eBo-X8FhGO1KtteC2nKxstewrz-Xs4_FTfnBvgCoNpV_ |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=proceeding&rft.title=Proceedings+-+Design%2C+Automation%2C+and+Test+in+Europe+Conference+and+Exhibition&rft.atitle=High-Throughput+SAT+Sampling&rft.au=Ardakani%2C+Arash&rft.au=Kang%2C+Minwoo&rft.au=He%2C+Kevin&rft.au=Huang%2C+Qijing&rft.date=2025-03-31&rft.pub=EDAA&rft.eissn=1558-1101&rft.spage=1&rft.epage=7&rft_id=info:doi/10.23919%2FDATE64628.2025.10993248&rft.externalDocID=10993248 |