On the Exploration of Convolutional Variational Autoencoders for Analog Integrated Circuit Post-Placement Performance Regression

The layout-aware synthesis of analog integrated circuits (ICs) still poses significant challenges, not only due to the inherent impact of parasitic structures and layout-dependent effects (LDEs) on the expected functional behavior, but also due to the computational effort required to conduct such op...

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Bibliographic Details
Published in:International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (Online) pp. 1 - 4
Main Authors: Almeida, Carlos, Oliveira, Marco, Martins, Ricardo
Format: Conference Proceeding
Language:English
Published: IEEE 07.07.2025
Subjects:
Analog integrated circuits
Analytical models
Autoencoders
Computational modeling
Design automation
Electronic Design Automation
Feature extraction
Integrated circuit modeling
Layout
Machine Learning
Optimization
Performance metrics
Performance Modeling
Post-layout Performance
ISSN:2575-4890
Online Access:Get full text
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Summary:The layout-aware synthesis of analog integrated circuits (ICs) still poses significant challenges, not only due to the inherent impact of parasitic structures and layout-dependent effects (LDEs) on the expected functional behavior, but also due to the computational effort required to conduct such optimizations. Therefore, this paper paves the way for the development of novel post-layout performance regressors, with the ultimate goal of bypassing time-consuming extractions and simulations. Here, deep learning (DL) models, namely convolutional variational autoencoders (VAEs) and multi-layer perceptrons (MLPs), are combined to extract essential floorplan features and learn the underlying relationship between placement and post-layout performance. Preliminary results reveal mean absolute percentage errors (MAPE) below 2% for five out of the six performance metrics considered for a typical analog structure, and below 1% for four, confirming its ability to generalize across unseen layouts.
ISSN:2575-4890
DOI:10.1109/SMACD65553.2025.11092107