A Frequency optimized architectural approach to lightweight authenticated encryption algorithm ACE-128
Communication stands out as a vital function facili tated by the Internet of Things (IoT), making the secure transfer of data from origin to destination crucial. Traditional encryption methods can accomplish this task, but they often require a trade off between cost, security, and efficiency. In con...
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| Vydáno v: | 2025 Fourth International Conference on Power, Control and Computing Technologies (ICPC2T) s. 1 - 6 |
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20.01.2025
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| Abstract | Communication stands out as a vital function facili tated by the Internet of Things (IoT), making the secure transfer of data from origin to destination crucial. Traditional encryption methods can accomplish this task, but they often require a trade off between cost, security, and efficiency. In contrast, lightweight encryption provides an effective balance of robust security, affordability, and enhanced performance. Moreover, the reduced data volume involved in lightweight encryption decreases the chances of successfully breaching the cipher. The ACE cipher, a 128-bit lightweight authenticated encryption algorithm, employs a 320-bit(40-bytes) internal state and operates in a unified sponge duplex configuration. The architecture proposed has been tested and implemented across various FPGA families, showcasing an increase in operational frequency. |
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| AbstractList | Communication stands out as a vital function facili tated by the Internet of Things (IoT), making the secure transfer of data from origin to destination crucial. Traditional encryption methods can accomplish this task, but they often require a trade off between cost, security, and efficiency. In contrast, lightweight encryption provides an effective balance of robust security, affordability, and enhanced performance. Moreover, the reduced data volume involved in lightweight encryption decreases the chances of successfully breaching the cipher. The ACE cipher, a 128-bit lightweight authenticated encryption algorithm, employs a 320-bit(40-bytes) internal state and operates in a unified sponge duplex configuration. The architecture proposed has been tested and implemented across various FPGA families, showcasing an increase in operational frequency. |
| Author | Srikanth, Medaboyina Patnaik, Bijayananda Acharya, Bibhudendra |
| Author_xml | – sequence: 1 givenname: Medaboyina surname: Srikanth fullname: Srikanth, Medaboyina email: msrikanth.mtech2023.etc@nitrr.ac.in organization: National Institute of Technology Raipur,Dept. of ECE,Raipur,India – sequence: 2 givenname: Bijayananda surname: Patnaik fullname: Patnaik, Bijayananda email: bpatnaik.etc@nitrr.ac.in organization: National Institute of Technology Raipur,Dept. of ECE,Raipur,India – sequence: 3 givenname: Bibhudendra surname: Acharya fullname: Acharya, Bibhudendra email: bacharya.etc@nitrr.ac.in organization: National Institute of Technology Raipur,Dept. of ECE,Raipur,India |
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| Snippet | Communication stands out as a vital function facili tated by the Internet of Things (IoT), making the secure transfer of data from origin to destination... |
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| SubjectTerms | ACE module ACE step Ciphers Embedded systems Encryption Internet of Things Lightweight cyrptography Performance evaluation Power control Protocols Reliability engineering resource constrained devices simeck-box(SB-64) Smart agriculture Vectors |
| Title | A Frequency optimized architectural approach to lightweight authenticated encryption algorithm ACE-128 |
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