CMOS VLSI Implementation of Implicit Pulsed Dual Edge Triggered Flip Flop using Pass Transistor Logic for Power Efficient Applications

In general, the flipflops are acting as a key circuit and major power intaking element in several digital systems modeling. In this work, a new power efficient flipflop topology titled Pass Transistor Logic based Implicit Pulsed - Dual Edge Triggered Flipflop (PTIP-DETFF) is offered, by fusing the p...

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Vydané v:2024 4th International Conference on Pervasive Computing and Social Networking (ICPCSN) s. 1019 - 1023
Hlavní autori: Nagarajan, P., Ashokkumar, N., Thandapani, Kavitha, Manimaran, B., Krishnamurthy, M., Kabilamani, P.
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 03.05.2024
Predmet:
CMOS technology
Delays
Distance measurement
dual edge triggering
flip flops
low power
Network topology
Pervasive computing
Social networking (online)
Topology
Very large scale integration
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Shrnutí:In general, the flipflops are acting as a key circuit and major power intaking element in several digital systems modeling. In this work, a new power efficient flipflop topology titled Pass Transistor Logic based Implicit Pulsed - Dual Edge Triggered Flipflop (PTIP-DETFF) is offered, by fusing the power minimization techniques such as minimum counts of device utilization, implicit pulsed clocking, dual edge triggering and parallel paradigm schemes. The implicit clock pulsing scheme eludes the exterior usage of clock generation network which intakes extra power. The twin edge triggering scheme halves the clock frequency which minimizes the dynamic power intake of flipflop as half. The parallel paradigm style diminishes the undesirable intake of power by the circuitry section which is not significant to result the preferred output. The offered flip flop topology is simulated using 0.12μm CMOS process technology and assessed in view of overall count of transistors, count of clock enabled loads, Layout area, Data in to output delay, entire power intake and also in terms of power delay product, Energy delay product and power energy products. The anticipated topology intakes the entire power of 5.265μW and achieves the power efficiency ranging from 12% to 63.30%, which conveys this anticipated flipflop will be appropriate for power efficient VLSI applications.
DOI:10.1109/ICPCSN62568.2024.00170