A Novel and Efficient SPI enabled RSA Crypto Accelerator for Real-Time applications - Kolagatla, Venkata Reddy; Raveendran, Aneesh; Desalphine, Vivian (International Symposium on VLSI Design and Test, 2024)
This paper presents the design, development and implementation of a novel and efficient Serial Peripheral Interface (SPI)-enabled Rivest-Shamir-Adleman (RSA) Encryption/Decryption Crypto Accelerator tailored for real-time applications. The RSA Crypto Accelerator was developed using the Semiconductor Laboratory (SCL) 180nm foundry Process Design Kit (PDK). This employs Cadence Genus and Innovus Electronic Design Automation (EDA) tools for synthesis and physical design, Siemens-EDA Calibre tools for physical verification, and Cadence Virtuoso with Spectre EDA tools for SPICE simulations and functional validation across corners. Key features include a total standard cell count of 1.15 million cells, operating at 1.8V for both the RSA Crypto core and Input/Output (IO) pads, with a power consumption of 1.43 W. The RSA core achieves an operational frequency of 100 MHz, synchronized with a 25 MHz SPI clock, ensuring efficient cryptographic performance. These features make the SPI-enabled RSA chip well-suited for real-time applications.