Towards Quantum Circuit Emulation on Low-Tier FPGAs

Researchers and industries are increasingly drawn to quantum computing for its computational potential. However, validating new quantum algorithms is challenging due to current quantum device limitations. Software simulators are time and memory-intensive, making hardware emulators an attractive alte...

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Vydáno v:2024 IEEE International Conference on Quantum Computing and Engineering (QCE) Ročník 2; s. 512 - 513
Hlavní autoři: Conti, Christian, Volpe, Deborah, Cirillo, Giovanni Amedeo, Graziano, Mariagrazia, Zamboni, Maurizio, Turvani, Giovanna
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 15.09.2024
Témata:
Computer architecture
Field Programmable Gate Array
Field programmable gate arrays
Hardware
Industries
Logic gates
Quantum algorithm
Quantum Algorithm Verification
Quantum circuit
Quantum Computing Emulation
Quantum Computing Simulation
Qubit
Software
Vectors
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Shrnutí:Researchers and industries are increasingly drawn to quantum computing for its computational potential. However, validating new quantum algorithms is challenging due to current quantum device limitations. Software simulators are time and memory-intensive, making hardware emulators an attractive alternative. This article introduces a digital architecture, designed to emulate quantum computing on low-tier Field-Programmable Gate Arrays (FPGAs), supporting Clifford+T and rotational gate sets. It simplifies and accelerates quantum algorithm verification using a RISC-like structure and efficiently handling sparse quantum gates. A dedicated compiler translates OpenQASM 2.0 into RISC-like instructions. The architecture is validated against the Qiskit state vector simulator, successfully emulating sixteen qubits on a Xilinx Kria KV260 SoM.
DOI:10.1109/QCE60285.2024.10381