FPGA based Filter Architecture for Image Processing Applications

In modern image acquisition and transmission, a crucial task is image denoising, particularly in fields like medical imaging (e.g., MRIs, CT scans, and ultrasounds) and surveillance (e.g., CCTV and video surveillance). The challenge lies in effectively locating and removing noise from images while p...

Full description

Saved in:

Bibliographic Details
Published in:	2024 4th International Conference on Pervasive Computing and Social Networking (ICPCSN) pp. 231 - 235
Main Authors:	C, Saranya, R, Kaviya, K, Keerthana A, M, Abishek
Format:	Conference Proceeding
Language:	English
Published:	IEEE 03.05.2024
Subjects:	Computer architecture Filters FPGA Image processing Median filter Noise Power demand PSNR Very large scale integration Video surveillance VLSI architecture
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Description
Summary:	In modern image acquisition and transmission, a crucial task is image denoising, particularly in fields like medical imaging (e.g., MRIs, CT scans, and ultrasounds) and surveillance (e.g., CCTV and video surveillance). The challenge lies in effectively locating and removing noise from images while preserving essential signal properties. To address this, a VLSI architecture is proposed, aiming to minimize noise in images while prioritizing speed. Unlike previous methods that relied on multipliers, the proposed approach utilizes distance matrix techniques for both bilateral and median filters. This technique not only reduces noise but also enhances processing speed, making the VLSI architecture more efficient. The proposed hardware design is implemented on a Spartan 6 FPGA kit to measure parameters such as power consumption, processing speed, and area usage, ensuring its practical viability and effectiveness.
DOI:	10.1109/ICPCSN62568.2024.00046