FPGA based Filter Architecture for Image Processing Applications

In modern image acquisition and transmission, a crucial task is image denoising, particularly in fields like medical imaging (e.g., MRIs, CT scans, and ultrasounds) and surveillance (e.g., CCTV and video surveillance). The challenge lies in effectively locating and removing noise from images while p...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:2024 4th International Conference on Pervasive Computing and Social Networking (ICPCSN) S. 231 - 235
Hauptverfasser: C, Saranya, R, Kaviya, K, Keerthana A, M, Abishek
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 03.05.2024
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Abstract In modern image acquisition and transmission, a crucial task is image denoising, particularly in fields like medical imaging (e.g., MRIs, CT scans, and ultrasounds) and surveillance (e.g., CCTV and video surveillance). The challenge lies in effectively locating and removing noise from images while preserving essential signal properties. To address this, a VLSI architecture is proposed, aiming to minimize noise in images while prioritizing speed. Unlike previous methods that relied on multipliers, the proposed approach utilizes distance matrix techniques for both bilateral and median filters. This technique not only reduces noise but also enhances processing speed, making the VLSI architecture more efficient. The proposed hardware design is implemented on a Spartan 6 FPGA kit to measure parameters such as power consumption, processing speed, and area usage, ensuring its practical viability and effectiveness.
AbstractList In modern image acquisition and transmission, a crucial task is image denoising, particularly in fields like medical imaging (e.g., MRIs, CT scans, and ultrasounds) and surveillance (e.g., CCTV and video surveillance). The challenge lies in effectively locating and removing noise from images while preserving essential signal properties. To address this, a VLSI architecture is proposed, aiming to minimize noise in images while prioritizing speed. Unlike previous methods that relied on multipliers, the proposed approach utilizes distance matrix techniques for both bilateral and median filters. This technique not only reduces noise but also enhances processing speed, making the VLSI architecture more efficient. The proposed hardware design is implemented on a Spartan 6 FPGA kit to measure parameters such as power consumption, processing speed, and area usage, ensuring its practical viability and effectiveness.
Author C, Saranya
K, Keerthana A
R, Kaviya
M, Abishek
Author_xml – sequence: 1
  givenname: Saranya
  surname: C
  fullname: C, Saranya
  email: saranyac@ksrct.ac.in
  organization: K. S. Rangasamy College of Technology,Department of Electronics and Communication Engineering,Tiruchengode,Tamil Nadu,India
– sequence: 2
  givenname: Kaviya
  surname: R
  fullname: R, Kaviya
  email: rtkaviyall@gmail.com
  organization: K. S. Rangasamy College of Technology,Department of Electronics and Communication Engineering,Tiruchengode,Tamil Nadu,India
– sequence: 3
  givenname: Keerthana A
  surname: K
  fullname: K, Keerthana A
  email: keerthanaak77@gmail.com
  organization: K. S. Rangasamy College of Technology,Department of Electronics and Communication Engineering,Tiruchengode,Tamil Nadu,India
– sequence: 4
  givenname: Abishek
  surname: M
  fullname: M, Abishek
  email: abisheksiva55555@gmail.com
  organization: K. S. Rangasamy College of Technology,Department of Electronics and Communication Engineering,Tiruchengode,Tamil Nadu,India
BookMark eNotzMtOg0AUANAxsQut_QNj5gfAOw_uDDsJkZakURLruhmYS52EAhlw4d-70NXZnXt2O04jMfYkIBUC8ue6bMqPN5QZ2lSC1CkAaLxhu9zkVmWgLCqd37GXqtkXvHULeV6FYaXIi9h9hZW69TsS76fI66u7EG_i1NGyhPHCi3keQufWMI3LA9v0blho9--WfVavp_KQHN_3dVkckyAMrkluhPOtxI6sUaikd4pa2WqPxuuMvPWZlQ40UKax9dJQT2QBySMRSlJb9vj3BiI6zzFcXfw5C0AwRln1CxqVSEE
CODEN IEEPAD
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/ICPCSN62568.2024.00046
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Xplore POP ALL
IEEE Xplore All Conference Proceedings
IEEE Xplore
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9798350386349
EndPage 235
ExternalDocumentID 10607738
Genre orig-research
GroupedDBID 6IE
6IL
CBEJK
RIE
RIL
ID FETCH-LOGICAL-i176t-971adb26ce873632da3eb2b4d67d45ed8d582a040e546bd27efee806ed6ee62e3
IEDL.DBID RIE
ISICitedReferencesCount 0
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=001289477900039&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Wed Aug 07 05:31:02 EDT 2024
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i176t-971adb26ce873632da3eb2b4d67d45ed8d582a040e546bd27efee806ed6ee62e3
PageCount 5
ParticipantIDs ieee_primary_10607738
PublicationCentury 2000
PublicationDate 2024-May-3
PublicationDateYYYYMMDD 2024-05-03
PublicationDate_xml – month: 05
  year: 2024
  text: 2024-May-3
  day: 03
PublicationDecade 2020
PublicationTitle 2024 4th International Conference on Pervasive Computing and Social Networking (ICPCSN)
PublicationTitleAbbrev ICPCSN
PublicationYear 2024
Publisher IEEE
Publisher_xml – name: IEEE
Score 1.8838818
Snippet In modern image acquisition and transmission, a crucial task is image denoising, particularly in fields like medical imaging (e.g., MRIs, CT scans, and...
SourceID ieee
SourceType Publisher
StartPage 231
SubjectTerms Computer architecture
Filters
FPGA
Image processing
Median filter
Noise
Power demand
PSNR
Very large scale integration
Video surveillance
VLSI architecture
Title FPGA based Filter Architecture for Image Processing Applications
URI https://ieeexplore.ieee.org/document/10607738
WOSCitedRecordID wos001289477900039&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV07TwMxDLZoxcAEiCLeysAauCa5JLdRVRx0qU4CpG5VLvFJHWhRafn9OOkBZWBgiyJFkW05tmN_NsB1QYGPcEZzk3vJVS00t6FQPGQ-1K6x0rksDZsw47GdTIqqBasnLAwipuIzvInLlMsPC7-OX2Wk4TozRtoOdIwxG7BWi_rtZ8XtaFgNn8bk0OtYsyVU6sSpf41NSVaj3P_nfQfQ-8HfserbshzCDs6P4K6sHgYsWp3AyllMcrPBVhaAkffJRq_0PLC2-J-OssFWfroHL-X98_CRt_MP-Kxv9IoTH10g7nm0RmopgpMUB9cqaBNUjsGG3ApHWoi50nUQBhtEm2kMGlELlMfQnS_meAJM9n3thM-KGBDWliRnyDKhasj7a8glOIVeJH_6tmlxMf2i_OyP_XPYixxOlX_yArqr5RovYdd_rGbvy6skmE_TwJCR
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LT8MwDI5gIMEJEEO8yYFroE3SJL0xTZRNjKoSQ9ptShtX2oENjY3fj5MVGAcO3KJIUWRbju3Yn03IdYqBD7daMZ1UgsmSK2ZcKpmLKlfa2ghrozBsQue5GY3SogGrBywMAITiM7jxy5DLd7Nq6b_KUMNVpLUwm2QrkZLHK7hWg_uNo_S23y26zzm69MpXbXEZenGqX4NTgt3I9v554z5p_yDwaPFtWw7IBkwPyV1WPHSotzuOZhOf5qadtTwARf-T9l_xgaBN-T8epZ21DHWbvGT3w26PNRMQ2CTWasGQk9Yh_yowWijBnRUYCZfSKe1kAs64xHCLegiJVKXjGmoAEylwCkBxEEekNZ1N4ZhQEVel5VWU-pCwNCg7jbYJZI3-X41OwQlpe_LHb6smF-Mvyk__2L8iO73h02A86OePZ2TXczvUAYpz0lrMl3BBtquPxeR9fhmE9AmKEZPY
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2024+4th+International+Conference+on+Pervasive+Computing+and+Social+Networking+%28ICPCSN%29&rft.atitle=FPGA+based+Filter+Architecture+for+Image+Processing+Applications&rft.au=C%2C+Saranya&rft.au=R%2C+Kaviya&rft.au=K%2C+Keerthana+A&rft.au=M%2C+Abishek&rft.date=2024-05-03&rft.pub=IEEE&rft.spage=231&rft.epage=235&rft_id=info:doi/10.1109%2FICPCSN62568.2024.00046&rft.externalDocID=10607738