An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm

A graph embedding is an emerging approach that can represent a graph structure with a fixed-length low-dimensional vector. node2vec is a well-known algorithm to obtain such a graph embedding by sampling neighboring nodes on a given graph with a random walk technique. However, the original node2vec a...

Full description

Saved in:
Bibliographic Details
Published in:2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) pp. 148 - 154
Main Authors: Sunaga, Kazuki, Sugiura, Keisuke, Matsutani, Hiroki
Format: Conference Proceeding
Language:English
Published: IEEE 27.05.2024
Subjects:
Accuracy
Conferences
Distributed processing
FPGA
Graph embedding
Heuristic algorithms
Internet of Things
node2vec
OS-ELM
Sequential training
Training
Vectors
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Abstract A graph embedding is an emerging approach that can represent a graph structure with a fixed-length low-dimensional vector. node2vec is a well-known algorithm to obtain such a graph embedding by sampling neighboring nodes on a given graph with a random walk technique. However, the original node2vec algorithm typically relies on a batch training of graph structures; thus, it is not suited for applications in which the graph structure changes after the deployment. In this paper, we focus on node2vec applications for IoT (Internet of Things) environments. To handle the changes of graph structures after the IoT devices have been deployed in edge environments, in this paper we propose to combine an online sequential training algorithm with node2vec. The proposed sequentially-trainable model is implemented on an FPGA (Field-Programmable Gate Array) device to demonstrate the benefits of our approach. The proposed FPGA implementation achieves up to 205.25 times speedup compared to the original model on ARM Cortex-A53 CPU. Evaluation results using dynamic graphs show that although the accuracy is decreased in the original model, the proposed sequential model can obtain better graph embedding that achieves a higher accuracy even when the graph structure is changed.
AbstractList A graph embedding is an emerging approach that can represent a graph structure with a fixed-length low-dimensional vector. node2vec is a well-known algorithm to obtain such a graph embedding by sampling neighboring nodes on a given graph with a random walk technique. However, the original node2vec algorithm typically relies on a batch training of graph structures; thus, it is not suited for applications in which the graph structure changes after the deployment. In this paper, we focus on node2vec applications for IoT (Internet of Things) environments. To handle the changes of graph structures after the IoT devices have been deployed in edge environments, in this paper we propose to combine an online sequential training algorithm with node2vec. The proposed sequentially-trainable model is implemented on an FPGA (Field-Programmable Gate Array) device to demonstrate the benefits of our approach. The proposed FPGA implementation achieves up to 205.25 times speedup compared to the original model on ARM Cortex-A53 CPU. Evaluation results using dynamic graphs show that although the accuracy is decreased in the original model, the proposed sequential model can obtain better graph embedding that achieves a higher accuracy even when the graph structure is changed.
Author Sugiura, Keisuke
Matsutani, Hiroki
Sunaga, Kazuki
Author_xml – sequence: 1
  givenname: Kazuki
  surname: Sunaga
  fullname: Sunaga, Kazuki
  email: sunaga@arc.ics.keio.ac.jp
  organization: Keio University,Yokohama,Japan,223-8522
– sequence: 2
  givenname: Keisuke
  surname: Sugiura
  fullname: Sugiura, Keisuke
  email: sugiura@arc.ics.keio.ac.jp
  organization: Keio University,Yokohama,Japan,223-8522
– sequence: 3
  givenname: Hiroki
  surname: Matsutani
  fullname: Matsutani, Hiroki
  email: matutani@arc.ics.keio.ac.jp
  organization: Keio University,Yokohama,Japan,223-8522
BookMark eNotjs9Kw0AYxFfQg9a-gUheIPHbv8keY21joWCkFY9l3f3SLiSbukkPvr0pepgZ-MEMc0euQx-QkEcKGaWgn9b1S739VJxSnTFgIgMAAVdkrnNdcAlcCQXqlryXIVnVVZk-mwFdUlqLLUYz9jFpJlXRnI7JsvtC53w4JOfh4lv8PmMYvWmTXTQ-XFjZHvrox2N3T24a0w44_88Z-Vgtd4vXdPNWrRflJvU0V2MqLQPtHC-YZVJoaxxgQY3SFnPXMMGFsFRy5rRVtjBUNMBlXjCkUunpDZ-Rh79dj4j7U_SdiT97ClIrMdV_AWfPTSQ
CODEN IEEPAD
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/IPDPSW63119.2024.00040
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Xplore POP ALL
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9798350364606
EndPage 154
ExternalDocumentID 10596424
Genre orig-research
GroupedDBID 6IE
6IL
CBEJK
RIE
RIL
ID FETCH-LOGICAL-i176t-5c209dd382c2549cad0e81a69ce7df24344c1532d9c6c8a14f035782e1569edd3
IEDL.DBID RIE
ISICitedReferencesCount 1
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=001284697300078&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Wed Jul 31 06:01:59 EDT 2024
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i176t-5c209dd382c2549cad0e81a69ce7df24344c1532d9c6c8a14f035782e1569edd3
PageCount 7
ParticipantIDs ieee_primary_10596424
PublicationCentury 2000
PublicationDate 2024-May-27
PublicationDateYYYYMMDD 2024-05-27
PublicationDate_xml – month: 05
  year: 2024
  text: 2024-May-27
  day: 27
PublicationDecade 2020
PublicationTitle 2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
PublicationTitleAbbrev IPDPSW
PublicationYear 2024
Publisher IEEE
Publisher_xml – name: IEEE
Score 1.8788693
Snippet A graph embedding is an emerging approach that can represent a graph structure with a fixed-length low-dimensional vector. node2vec is a well-known algorithm...
SourceID ieee
SourceType Publisher
StartPage 148
SubjectTerms Accuracy
Conferences
Distributed processing
FPGA
Graph embedding
Heuristic algorithms
Internet of Things
node2vec
OS-ELM
Sequential training
Training
Vectors
Title An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm
URI https://ieeexplore.ieee.org/document/10596424
WOSCitedRecordID wos001284697300078&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV09T8MwELVoxcAEiCK-5YHVNI5df4wB2sJSBbWIblViO6VSm6CS8vs5uwHEwMAWWYosvSh-73z37hC6VtpoYJqcWM1yAorYkryIOQGxLDkvWNGzURg2IUcjNZ3qtDGrBy-Mcy4Un7kb_xhy-bYyG39V1vVaAPQyb6GWlGJr1mpcvzTS3cf0Ph2_CEapd6DEPHTijH6NTQmsMdj_534HqPPjv8PpN7Mcoh1XHqGnpMSDdJiQWyAeixNjgDFCkhyD8MRD33ka91e5s_4l7Ava53gcKqXhL17iSTMMAifLebVe1K-rDnoe9Cd3D6QZiEAWVIqa9EwcaWuZio2P60xmI6doJrRx0gLCjHMDJ1hstRFGZZQXkW9mEzsI0jTszo5Ru6xKd4JwroDHc2U1HLzcah8ICwCrEMwImVFzijoej9nbtufF7AuKsz_Wz9Geh9zn1WN5gdr1euMu0a75qBfv66vwpT4BmZuVSw
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PT8IwFG4UTfSkRoy_7cFrZe1K1x6nghCRzICRG9naDklgGBz-_b7WqfHgwdvSZGnyLev3Xt_73ofQpVRaAdNkxKgwIxARG5LljBMIliPO8zBvmsCbTUT9vhyNVFKJ1b0Wxlrrm8_slXv0tXyz0Ct3VdZwsQDEy3wdbTjrrEquVel-aaAa3eQ2GTyLkFKnQWHcz-IMfhmneN5o7_xzx11U_1Hg4eSbW_bQmi320WNc4HZyF5NroB6DY62BM3yZHEPoie_c7GncmmfWuJewa2mf4IHvlYb_eIaHlR0EjmeTxXJavszr6KndGt50SGWJQKY0EiVpahYoY0LJtMvsdGoCK2kqlLaRAYxDzjWcYcwoLbRMKc8DN86GWUjTFOweHqBasSjsIcKZBCbPpFFw9HKjXCosAKxchFpEKdVHqO7wGL9-Tr0Yf0Fx_Mf6BdrqDB964163f3-Cth38rsrOolNUK5cre4Y29Xs5fVue-6_2AZFumJQ
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2024+IEEE+International+Parallel+and+Distributed+Processing+Symposium+Workshops+%28IPDPSW%29&rft.atitle=An+FPGA-Based+Accelerator+for+Graph+Embedding+using+Sequential+Training+Algorithm&rft.au=Sunaga%2C+Kazuki&rft.au=Sugiura%2C+Keisuke&rft.au=Matsutani%2C+Hiroki&rft.date=2024-05-27&rft.pub=IEEE&rft.spage=148&rft.epage=154&rft_id=info:doi/10.1109%2FIPDPSW63119.2024.00040&rft.externalDocID=10596424