A gm/ID Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

This article presents a methodology for sizing transistors of a multistage, multipath capacitor-less feed-forward compensated operational amplifiers employed in advanced CMOS process implementation of continuous-time bandpass <inline-formula> <tex-math notation="LaTeX">\Sigma \...

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Vydáno v:IEEE transactions on computer-aided design of integrated circuits and systems Ročník 39; číslo 12; s. 4311 - 4324
Hlavní autoři: Gebreyohannes, Fikre Tsigabu, Porte, Jacky, Louerat, Marie-Minerve, Aboushady, Hassan
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.12.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">gm /<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">iD methodology
Amplification
Amplifier design
Bandpass
Capacitors
Circuits
CMOS
Continuous time
Data search
feed-forward compensation
Frequency modulation
Frequency response
Gain
Mathematical model
MATLAB script
Methodology
Modulators
multipath
multistage
operational amplifier
Operational amplifiers
Performance measurement
Poles and zeros
search algorithm
Search algorithms
Semiconductor devices
sigma delta modulator
Sizing
Transistors
ISSN:0278-0070, 1937-4151
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Shrnutí:This article presents a methodology for sizing transistors of a multistage, multipath capacitor-less feed-forward compensated operational amplifiers employed in advanced CMOS process implementation of continuous-time bandpass <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula>-modulators. This article describes the methodology: on system level, dealing with the placement of poles and zeros; and on the circuit level, discussing issues related to biasing, frequency response and other important performance metrics of the basic diff-pair. Algorithms are provided to simplify mathematical aspects of the work. The validity and the limitations of the proposed methodology are further discussed from the single-pole system used to model the individual amplification stages of the multistage amplifier. The worthiness of the proposed methodology in sizing the transistors of complex amplifier structures, such as the capacitor-less multistage, multipath feed-forward-compensated amplifiers is demonstrated using two design examples. A third-order amplifier with a dc gain of 52.6 dB and that reaches a unity-gain frequency of above 14 GHz while consuming only 5.6 mA from a 1-V supply; and a fourth-order amplifier with dc gain of 73.5 dB that achieves a 25.7-dB gain at 1 GHz while consuming 4.8 mW are designed in 28-nm CMOS FDSOI.
Bibliografie:ObjectType-Article-1
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content type line 14
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2020.2966998