High throughput implementations of cryptography algorithms on GPU and FPGA

Cryptography algorithms are ranked by their speed in encrypting/decrypting data and their robustness to withstand attacks. Real-time processing of data encryption/decryption is essential in network based applications to keep pace with the input data inhalation rate. The encryption/decryption steps a...

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Published in:2013 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) pp. 723 - 727
Main Authors: Venugopal, Vivek, Shila, Devu Manikantan
Format: Conference Proceeding
Language:English
Published: IEEE 01.05.2013
Subjects:
cryptography
Encryption
Field programmable gate arrays
Graphics processing units
Hardware
Logic gates
parallel processing
Throughput
Tiny Encryption Algorithm
ISBN:9781467346214, 1467346217
ISSN:1091-5281
Online Access:Get full text
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Abstract Cryptography algorithms are ranked by their speed in encrypting/decrypting data and their robustness to withstand attacks. Real-time processing of data encryption/decryption is essential in network based applications to keep pace with the input data inhalation rate. The encryption/decryption steps are computationally intensive and exhibit high degree of parallelism. Field programmable gate arrays (FPGA) and graphics processing units (GPU) are being employed as cryptographic coprocessors to target different cryptography algorithms. In this paper, we target different encryption algorithms (TEA and XTEA) on GPU and FPGA platforms. We investigate the performance of the algorithms in terms of latency, throughput, gate equivalence, cost and ease of mapping on both platforms. We employ optimization techniques to realize high throughput in our custom configured implementations for coarse-grained parallel architectures. We propose a tool called Cryptographic Hardware Acceleration and Analysis Tool (CHAAT) that selects an optimal algorithm depending on the user's constraints with respect to hardware utilization, cost and security.
AbstractList Cryptography algorithms are ranked by their speed in encrypting/decrypting data and their robustness to withstand attacks. Real-time processing of data encryption/decryption is essential in network based applications to keep pace with the input data inhalation rate. The encryption/decryption steps are computationally intensive and exhibit high degree of parallelism. Field programmable gate arrays (FPGA) and graphics processing units (GPU) are being employed as cryptographic coprocessors to target different cryptography algorithms. In this paper, we target different encryption algorithms (TEA and XTEA) on GPU and FPGA platforms. We investigate the performance of the algorithms in terms of latency, throughput, gate equivalence, cost and ease of mapping on both platforms. We employ optimization techniques to realize high throughput in our custom configured implementations for coarse-grained parallel architectures. We propose a tool called Cryptographic Hardware Acceleration and Analysis Tool (CHAAT) that selects an optimal algorithm depending on the user's constraints with respect to hardware utilization, cost and security.
Author Venugopal, Vivek
Shila, Devu Manikantan
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  givenname: Devu Manikantan
  surname: Shila
  fullname: Shila, Devu Manikantan
  email: manikad@utrc.utc.com
  organization: United Technologies Research Center, 411 Silver Lane, E Hartford, CT USA
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Snippet Cryptography algorithms are ranked by their speed in encrypting/decrypting data and their robustness to withstand attacks. Real-time processing of data...
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StartPage 723
SubjectTerms cryptography
Encryption
Field programmable gate arrays
Graphics processing units
Hardware
Logic gates
parallel processing
Throughput
Tiny Encryption Algorithm
Title High throughput implementations of cryptography algorithms on GPU and FPGA
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