Reducing data transfer latency of NAND flash memory with soft-decision sensing
With the aggressive technology scaling and use of multi-bit per cell storage, NAND flash memory is subject to continuous degradation of raw storage reliability and demands more and more powerful error correction codes (ECC). This inevitable trend makes conventional BCH code increasingly inadequate,...
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| Vydáno v: | 2012 IEEE International Conference on Communications (ICC) s. 7024 - 7028 |
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| Hlavní autoři: | , , |
| Médium: | Konferenční příspěvek |
| Jazyk: | angličtina |
| Vydáno: |
IEEE
01.06.2012
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| Témata: | |
| ISBN: | 9781457720529, 1457720523 |
| ISSN: | 1550-3607 |
| On-line přístup: | Získat plný text |
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| Shrnutí: | With the aggressive technology scaling and use of multi-bit per cell storage, NAND flash memory is subject to continuous degradation of raw storage reliability and demands more and more powerful error correction codes (ECC). This inevitable trend makes conventional BCH code increasingly inadequate, and iterative coding solutions such as LDPC codes become very natural alternative options. However, these powerful coding solutions demand soft-decision memory sensing, which results in longer on-chip memory sensing latency and memory-to-controller data transfer latency. This paper presents two simple design techniques that can reduce the memory-to-controller data transfer latency. The key is to appropriately apply entropy coding to compress the memory sensing results. Simulation results show that the proposed design solutions can reduce the data transfer latency by up to 64% for soft-decision memory sensing. |
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| ISBN: | 9781457720529 1457720523 |
| ISSN: | 1550-3607 |
| DOI: | 10.1109/ICC.2012.6364887 |