Efficient one-pass chase soft-decision BCH decoder for multi-level cell NAND flash memory

BCH codes are adopted in multi-level cell NAND flash memory to increase the storage reliability. Compared with hard-decision decoding of BCH codes, the soft-decision Chase algorithm can achieve significant coding gain by carrying out decoding trials on 2 η test vectors. To reduce the complexity of t...

Celý popis

Uložené v:
Podrobná bibliografia
Vydané v:2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) s. 1 - 4
Hlavní autori: Xinmiao Zhang, Jiangli Zhu, Yingquan Wu
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 01.08.2011
Predmet:
Computer architecture
Decoding
Logic gates
ISBN:9781612848563, 1612848567
ISSN:1548-3746
On-line prístup:Získať plný text
Tagy: Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
Abstract BCH codes are adopted in multi-level cell NAND flash memory to increase the storage reliability. Compared with hard-decision decoding of BCH codes, the soft-decision Chase algorithm can achieve significant coding gain by carrying out decoding trials on 2 η test vectors. To reduce the complexity of the Chase decoding, a one-pass scheme can be employed to derive the error locators of all test vectors in one run. In this paper, a novel technique is first proposed to reduce the latency and simplify the computation scheduling of the one-pass Chase decoding. Then efficient architectures are developed for the modified one-pass decoding. The hardware complexity of the proposed decoder with η = 4 is analyzed for a (4200, 4096) BCH code. Compared to other soft-decision BCH decoding algorithms, it can achieve much better performance-complexity tradeoff.
AbstractList BCH codes are adopted in multi-level cell NAND flash memory to increase the storage reliability. Compared with hard-decision decoding of BCH codes, the soft-decision Chase algorithm can achieve significant coding gain by carrying out decoding trials on 2 η test vectors. To reduce the complexity of the Chase decoding, a one-pass scheme can be employed to derive the error locators of all test vectors in one run. In this paper, a novel technique is first proposed to reduce the latency and simplify the computation scheduling of the one-pass Chase decoding. Then efficient architectures are developed for the modified one-pass decoding. The hardware complexity of the proposed decoder with η = 4 is analyzed for a (4200, 4096) BCH code. Compared to other soft-decision BCH decoding algorithms, it can achieve much better performance-complexity tradeoff.
Author Jiangli Zhu
Yingquan Wu
Xinmiao Zhang
Author_xml – sequence: 1
  surname: Xinmiao Zhang
  fullname: Xinmiao Zhang
  email: xinmiao.zhang@case.edu
– sequence: 2
  surname: Jiangli Zhu
  fullname: Jiangli Zhu
  email: jiangli.zhu@case.edu
– sequence: 3
  surname: Yingquan Wu
  fullname: Yingquan Wu
  email: yingquan_wu@yahoo.com
BookMark eNo1kM1KAzEURiNWsK19gm7yAqm5yUySWdax_kCtiyriqmQmNzSSmSmTUejbW7CuPs7mO3AmZNR2LRIyB74A4MXty8e2XG4XggMsFBdK5tkFmYACYTKT6_ySzApt_lnJERlDnhkmdaauySSlL86F1FCMyefK-1AHbAd6crCDTYnWe5uQps4PzGEdUuhaelc-0RN0Dnvqu54233EILOIPRlpjjHSz3NxTH23a0wabrj_ekCtvY8LZeafk_WH1Vj6x9evjc7lcswA6H5g3HBVClqMDczIUzuSVMLqwwiuls6qSFXhVcckdl5YbIwquvHFe1yAcyimZ__0GRNwd-tDY_rg7Z5G_kINWVw
ContentType Conference Proceeding
DBID 6IE
6IH
CBEJK
RIE
RIO
DOI 10.1109/MWSCAS.2011.6026354
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan (POP) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP) 1998-present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EISBN 1612848575
9781612848570
9781612848556
1612848559
EndPage 4
ExternalDocumentID 6026354
Genre orig-research
GroupedDBID 29B
29F
6IE
6IF
6IH
6IK
6IL
6IM
6IN
AAJGR
AAWTH
ABLEC
ACGFS
ADZIZ
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
CHZPO
IEGSK
IJVOP
IPLJI
M43
OCL
RIE
RIL
RIO
RNS
ID FETCH-LOGICAL-i175t-f80e6e145ed18dec9d85b2879a2f6674bb3b1f6b030d03a0882906f8df7c12de3
IEDL.DBID RIE
ISBN 9781612848563
1612848567
ISICitedReferencesCount 0
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000296057200091&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
ISSN 1548-3746
IngestDate Wed Aug 27 02:43:31 EDT 2025
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i175t-f80e6e145ed18dec9d85b2879a2f6674bb3b1f6b030d03a0882906f8df7c12de3
PageCount 4
ParticipantIDs ieee_primary_6026354
PublicationCentury 2000
PublicationDate 2011-Aug.
PublicationDateYYYYMMDD 2011-08-01
PublicationDate_xml – month: 08
  year: 2011
  text: 2011-Aug.
PublicationDecade 2010
PublicationTitle 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)
PublicationTitleAbbrev MWSCAS
PublicationYear 2011
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0023719
ssj0000668878
Score 1.810653
Snippet BCH codes are adopted in multi-level cell NAND flash memory to increase the storage reliability. Compared with hard-decision decoding of BCH codes, the...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms Computer architecture
Decoding
Logic gates
Title Efficient one-pass chase soft-decision BCH decoder for multi-level cell NAND flash memory
URI https://ieeexplore.ieee.org/document/6026354
WOSCitedRecordID wos000296057200091&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3NT8IwFG-AeNCLH2D8Tg8erWzr2q1HRAgHXUjQiCfSrm0gUSB8mPjf-1rG1MSLt3VJu6Yv7fvt9b3fD6FrG0imrGUkT7khsZGSSGsYYUoKcH95yJTnmX1IsiwdDkW_gm7KWhhjjE8-M7fu0d_l61m-dqGyppNLoiyuomqS8E2tVhlPAdcJ-6W8QYho4kU9HCKHTRRzV9TF3WGcMp4UXE_bNi3oiMJANB9fBu3WYMPtWXzvl_CK9zvd_f_N-AA1vgv4cL90TYeoYqZHaO8H92AdvXY8eQR0x7OpIXMA0Tgfg0_DSziZiS60d_Bdu4eh4STTMABc7DMQyZvLNcIu6o-zVnaPLYDwMX53abufDfTc7Ty1e6TQWSATAA8rYtPAcBPGzOgwhRGFTpmCPykhI8t5EitFVWi5gvNAB1Q6UC4CblNtwZaRNvQY1aYw1ROEqZA0Z0pJo_OYg72FhYG4jpUMEhnJU1R3izSab6g0RsX6nP39-hztbkO4QXiBaqvF2lyinfxjNVkurrz9vwBuu6qu
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LTwIxEG4QTdSLDzS-7cGjlX203e0REYIRNiRgxBNpt20gUSA8TPz3TpcFNfHibbvJdpt2O_PtdOb7ELqxnmTKWkbSmBtCjZREWsMIU1KA-0t9pjKe2WaUJHGvJ9oFdLuuhTHGZMln5s5dZmf5epwuXKis7OSSQkY30CajNPCW1VrriAo4T9gx6zOEIIwyWQ-HyWEbUe7KurgzxzHjUc72tGqHOSGR74ly66VTrXSW7J75G39Jr2Sep773vzHvo6PvEj7cXjunA1Qwo0O0-4N9sIReaxl9BDyOxyNDJgCjcToAr4ZnYJuJztV38H21gaHhRNMwQFyc5SCSN5dthF3cHyeV5AFbgOED_O4Sdz-P0HO91q02SK60QIYAH-bExp7hxqfMaD-GHoWOmYJ_KSEDy3lElQqVb7kCi6C9UDpYLjxuY21hNQNtwmNUHMFQTxAOhQxTppQ0OqUcVlxY6IhrqqQXyUCeopKbpP5kSabRz-fn7O_b12i70W01-83H5Okc7awCup5_gYrz6cJcoq30Yz6cTa-yb-ELhYqt9Q
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2011+IEEE+54th+International+Midwest+Symposium+on+Circuits+and+Systems+%28MWSCAS%29&rft.atitle=Efficient+one-pass+chase+soft-decision+BCH+decoder+for+multi-level+cell+NAND+flash+memory&rft.au=Xinmiao+Zhang&rft.au=Jiangli+Zhu&rft.au=Yingquan+Wu&rft.date=2011-08-01&rft.pub=IEEE&rft.isbn=9781612848563&rft.issn=1548-3746&rft.spage=1&rft.epage=4&rft_id=info:doi/10.1109%2FMWSCAS.2011.6026354&rft.externalDocID=6026354
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1548-3746&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1548-3746&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1548-3746&client=summon