Minimizing Communication in All-Pairs Shortest Paths

We consider distributed memory algorithms for the all-pairs shortest paths (APSP) problem. Scaling the APSP problem to high concurrencies requires both minimizing inter-processor communication as well as maximizing temporal data locality. The 2.5D APSP algorithm, which is based on the divide-and-con...

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Veröffentlicht in:2013 IEEE 27th International Symposium on Parallel and Distributed Processing S. 548 - 559
Hauptverfasser: Solomonik, Edgar, Buluç, Aydın, Demmel, James
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.05.2013
Schlagworte:
2.5D algorithms
Algorithm design and analysis
all-pairs shortest paths
Bandwidth
communication-avoiding algorithms
Heuristic algorithms
Matrix decomposition
Particle separators
Partitioning algorithms
ISBN:146736066X, 9781467360661
ISSN:1530-2075
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Zusammenfassung:We consider distributed memory algorithms for the all-pairs shortest paths (APSP) problem. Scaling the APSP problem to high concurrencies requires both minimizing inter-processor communication as well as maximizing temporal data locality. The 2.5D APSP algorithm, which is based on the divide-and-conquer paradigm, satisfies both of these requirements: it can utilize any extra available memory to perform asymptotically less communication, and it is rich in semiring matrix multiplications, which have high temporal locality. We start by introducing a block-cyclic 2D (minimal memory) APSP algorithm. With a careful choice of block-size, this algorithm achieves known communication lower-bounds for latency and bandwidth. We extend this 2D block-cyclic algorithm to a 2.5D algorithm, which can use c extra copies of data to reduce the bandwidth cost by a factor of c 1/2 , compared to its 2D counterpart. However, the 2.5D algorithm increases the latency cost by c 1/2 . We provide a tighter lower bound on latency, which dictates that the latency overhead is necessary to reduce bandwidth along the critical path of execution. Our implementation achieves impressive performance and scaling to 24,576 cores of a Cray XE6 supercomputer by utilizing well-tuned intra-node kernels within the distributed memory algorithm.
ISBN:146736066X
9781467360661
ISSN:1530-2075
DOI:10.1109/IPDPS.2013.111