System-Level Retiming and Pipelining

In this paper, we examine retiming and pipelining in the context of system-level optimization techniques. Our main contributions are: (a) functionally equivalent retiming and delay balancing as necessary techniques for pipelining and retiming system-level graphs while maintaining numerical fidelity,...

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Vydáno v:	2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines s. 80 - 87
Hlavní autoři:	Venkataramani, Girish, Yongfeng Gu
Médium:	Konferenční příspěvek
Jazyk:	angličtina
Vydáno:	IEEE 01.05.2014
Témata:	Algorithm design and analysis Delays Hardware design languages high-level synthesis ESL pipelining retiming multi-cycle Simulink HDL Coder MATLAB Pipeline processing Registers Software packages
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Popis
Shrnutí:	In this paper, we examine retiming and pipelining in the context of system-level optimization techniques. Our main contributions are: (a) functionally equivalent retiming and delay balancing as necessary techniques for pipelining and retiming system-level graphs while maintaining numerical fidelity, and (b) clock-rate pipelining, as a new technique that leverages the knowledge of multi-rate design spec to pipeline multi-cycle paths. All these techniques have been implemented within HDL Coder™, a tool that generates synthesizable HDL code from Simulink ® and MATLAB®.
DOI:	10.1109/FCCM.2014.30