System-Level Retiming and Pipelining

In this paper, we examine retiming and pipelining in the context of system-level optimization techniques. Our main contributions are: (a) functionally equivalent retiming and delay balancing as necessary techniques for pipelining and retiming system-level graphs while maintaining numerical fidelity,...

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Vydané v:2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines s. 80 - 87
Hlavní autori: Venkataramani, Girish, Yongfeng Gu
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 01.05.2014
Predmet:
Algorithm design and analysis
Delays
Hardware design languages
high-level synthesis ESL pipelining retiming multi-cycle Simulink HDL Coder MATLAB
Pipeline processing
Registers
Software packages
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Abstract In this paper, we examine retiming and pipelining in the context of system-level optimization techniques. Our main contributions are: (a) functionally equivalent retiming and delay balancing as necessary techniques for pipelining and retiming system-level graphs while maintaining numerical fidelity, and (b) clock-rate pipelining, as a new technique that leverages the knowledge of multi-rate design spec to pipeline multi-cycle paths. All these techniques have been implemented within HDL Coder™, a tool that generates synthesizable HDL code from Simulink ® and MATLAB®.
AbstractList In this paper, we examine retiming and pipelining in the context of system-level optimization techniques. Our main contributions are: (a) functionally equivalent retiming and delay balancing as necessary techniques for pipelining and retiming system-level graphs while maintaining numerical fidelity, and (b) clock-rate pipelining, as a new technique that leverages the knowledge of multi-rate design spec to pipeline multi-cycle paths. All these techniques have been implemented within HDL Coder™, a tool that generates synthesizable HDL code from Simulink ® and MATLAB®.
Author Yongfeng Gu
Venkataramani, Girish
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  organization: MathWorks, Inc., Natick, MA, USA
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  surname: Yongfeng Gu
  fullname: Yongfeng Gu
  email: ygu@mathworks.com
  organization: MathWorks, Inc., Natick, MA, USA
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Snippet In this paper, we examine retiming and pipelining in the context of system-level optimization techniques. Our main contributions are: (a) functionally...
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StartPage 80
SubjectTerms Algorithm design and analysis
Delays
Hardware design languages
high-level synthesis ESL pipelining retiming multi-cycle Simulink HDL Coder MATLAB
Pipeline processing
Registers
Software packages
Title System-Level Retiming and Pipelining
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