Hardware efficient frequency estimator based on data-aided algorithm for digital video broadcasting system

This paper presents an efficient frequency estimator for digital video broadcasting - second generation (DVB-S2). Analyzing the robust algorithm among data-aided approaches, we find that the Luise & Reggiannini (L&R) algorithm is the most suitable one for coarse frequency estimation with res...

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Vydáno v:APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems s. 890 - 893
Hlavní autoři: Ryu, C.D., Park, J.W., Myung Hoon Sunwoo, Pan Soo Kim, Dae-Ig Chang
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.11.2008
Témata:
Adders
Algorithm design and analysis
Computer architecture
Correlators
Digital video broadcasting
Frequency estimation
Hardware
Multiplexing
Performance analysis
Robustness
ISBN:9781424423415, 1424423414
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Abstract This paper presents an efficient frequency estimator for digital video broadcasting - second generation (DVB-S2). Analyzing the robust algorithm among data-aided approaches, we find that the Luise & Reggiannini (L&R) algorithm is the most suitable one for coarse frequency estimation with respect to estimation performance and complexity. However, it requires many multipliers and adders to compute output values of correlators. We propose an efficient architecture identifying the serial correlator with the buffer and multiplexers. The proposed coarse frequency estimator can reduce the hardware complexity about 92% of the direct implementation. The proposed architecture has been implemented and verified on the Xilinx Virtex II FPGA.
AbstractList This paper presents an efficient frequency estimator for digital video broadcasting - second generation (DVB-S2). Analyzing the robust algorithm among data-aided approaches, we find that the Luise & Reggiannini (L&R) algorithm is the most suitable one for coarse frequency estimation with respect to estimation performance and complexity. However, it requires many multipliers and adders to compute output values of correlators. We propose an efficient architecture identifying the serial correlator with the buffer and multiplexers. The proposed coarse frequency estimator can reduce the hardware complexity about 92% of the direct implementation. The proposed architecture has been implemented and verified on the Xilinx Virtex II FPGA.
Author Pan Soo Kim
Dae-Ig Chang
Park, J.W.
Ryu, C.D.
Myung Hoon Sunwoo
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  surname: Ryu
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  givenname: J.W.
  surname: Park
  fullname: Park, J.W.
  organization: Sch. of Electr. & Comput. Eng., Ajou Univ., Suwon
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  surname: Myung Hoon Sunwoo
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  organization: Sch. of Electr. & Comput. Eng., Ajou Univ., Suwon
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  surname: Pan Soo Kim
  fullname: Pan Soo Kim
  organization: Broadband Wireless Multimedia Res. Team, Electr. & Telecommun. Res. Inst., Daejeon
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  surname: Dae-Ig Chang
  fullname: Dae-Ig Chang
  organization: Broadband Wireless Multimedia Res. Team, Electr. & Telecommun. Res. Inst., Daejeon
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Snippet This paper presents an efficient frequency estimator for digital video broadcasting - second generation (DVB-S2). Analyzing the robust algorithm among...
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SubjectTerms Adders
Algorithm design and analysis
Computer architecture
Correlators
Digital video broadcasting
Frequency estimation
Hardware
Multiplexing
Performance analysis
Robustness
Title Hardware efficient frequency estimator based on data-aided algorithm for digital video broadcasting system
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