Hardware efficient frequency estimator based on data-aided algorithm for digital video broadcasting system

This paper presents an efficient frequency estimator for digital video broadcasting - second generation (DVB-S2). Analyzing the robust algorithm among data-aided approaches, we find that the Luise & Reggiannini (L&R) algorithm is the most suitable one for coarse frequency estimation with res...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems S. 890 - 893
Hauptverfasser: Ryu, C.D., Park, J.W., Myung Hoon Sunwoo, Pan Soo Kim, Dae-Ig Chang
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.11.2008
Schlagworte:
Adders
Algorithm design and analysis
Computer architecture
Correlators
Digital video broadcasting
Frequency estimation
Hardware
Multiplexing
Performance analysis
Robustness
ISBN:9781424423415, 1424423414
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:This paper presents an efficient frequency estimator for digital video broadcasting - second generation (DVB-S2). Analyzing the robust algorithm among data-aided approaches, we find that the Luise & Reggiannini (L&R) algorithm is the most suitable one for coarse frequency estimation with respect to estimation performance and complexity. However, it requires many multipliers and adders to compute output values of correlators. We propose an efficient architecture identifying the serial correlator with the buffer and multiplexers. The proposed coarse frequency estimator can reduce the hardware complexity about 92% of the direct implementation. The proposed architecture has been implemented and verified on the Xilinx Virtex II FPGA.
ISBN:9781424423415
1424423414
DOI:10.1109/APCCAS.2008.4746166